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40 * Authors: Steve Reinhardt
43 #ifndef __ARCH_MIPS_LOCKED_MEM_HH__
44 #define __ARCH_MIPS_LOCKED_MEM_HH__
49 * ISA-specific helper functions for locked memory accesses.
52 #include "arch/registers.hh"
53 #include "base/misc.hh"
54 #include "base/trace.hh"
55 #include "debug/LLSC.hh"
56 #include "mem/packet.hh"
57 #include "mem/request.hh"
63 handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
65 if (!xc->readMiscReg(MISCREG_LLFLAG))
68 Addr locked_addr = xc->readMiscReg(MISCREG_LLADDR) & cacheBlockMask;
69 Addr snoop_addr = pkt->getAddr();
71 assert((cacheBlockMask & snoop_addr) == snoop_addr);
73 if (locked_addr == snoop_addr)
74 xc->setMiscReg(MISCREG_LLFLAG, false);
80 handleLockedRead(XC *xc, Request *req)
82 xc->setMiscReg(MISCREG_LLADDR, req->getPaddr() & ~0xf);
83 xc->setMiscReg(MISCREG_LLFLAG, true);
84 DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link"
85 " Address set to %x.\n",
86 req->threadId(), req->getPaddr() & ~0xf);
91 handleLockedSnoopHit(XC *xc)
97 handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
99 if (req->isUncacheable()) {
100 // Funky Turbolaser mailbox access...don't update
101 // result register (see stq_c in decoder.isa)
102 req->setExtraData(2);
104 // standard store conditional
105 bool lock_flag = xc->readMiscReg(MISCREG_LLFLAG);
106 Addr lock_addr = xc->readMiscReg(MISCREG_LLADDR);
108 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
109 // Lock flag not set or addr mismatch in CPU;
110 // don't even bother sending to memory system
111 req->setExtraData(0);
112 xc->setMiscReg(MISCREG_LLFLAG, false);
114 // the rest of this code is not architectural;
115 // it's just a debugging aid to help detect
116 // livelock by warning on long sequences of failed
117 // store conditionals
118 int stCondFailures = xc->readStCondFailures();
120 xc->setStCondFailures(stCondFailures);
121 if (stCondFailures % 100000 == 0) {
122 warn("%i: context %d: %d consecutive "
123 "store conditional failures\n",
124 curTick(), xc->contextId(), stCondFailures);
128 DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, "
129 "Store Conditional Failed.\n",
131 } else if ((req->getPaddr() & ~0xf) != lock_addr) {
132 DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, "
133 "Store Conditional Failed.\n",
136 // store conditional failed already, so don't issue it to mem
144 } // namespace MipsISA