src/arch/mips/locked_mem.hh

   1 /*
   2  * Copyright (c) 2006-2007 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  */
  30
  31 #ifndef __ARCH_MIPS_LOCKED_MEM_HH__
  32 #define __ARCH_MIPS_LOCKED_MEM_HH__
  33
  34 /**
  35  * @file
  36  *
  37  * ISA-specific helper functions for locked memory accesses.
  38  */
  39
  40 #include "arch/registers.hh"
  41 #include "base/misc.hh"
  42 #include "base/trace.hh"
  43 #include "mem/request.hh"
  44
  45
  46 namespace MipsISA
  47 {
  48 template <class XC>
  49 inline void
  50 handleLockedRead(XC *xc, Request *req)
  51 {
  52     xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf);
  53     xc->setMiscRegNoEffect(LLFlag, true);
  54     DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link Address set to %x.\n",
  55             req->threadId(), req->getPaddr() & ~0xf);
  56 }
  57
  58
  59 template <class XC>
  60 inline bool
  61 handleLockedWrite(XC *xc, Request *req)
  62 {
  63     if (req->isUncacheable()) {
  64         // Funky Turbolaser mailbox access...don't update
  65         // result register (see stq_c in decoder.isa)
  66         req->setExtraData(2);
  67     } else {
  68         // standard store conditional
  69         bool lock_flag = xc->readMiscRegNoEffect(LLFlag);
  70         Addr lock_addr = xc->readMiscRegNoEffect(LLAddr);
  71
  72         if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
  73             // Lock flag not set or addr mismatch in CPU;
  74             // don't even bother sending to memory system
  75             req->setExtraData(0);
  76             xc->setMiscRegNoEffect(LLFlag, false);
  77
  78             // the rest of this code is not architectural;
  79             // it's just a debugging aid to help detect
  80             // livelock by warning on long sequences of failed
  81             // store conditionals
  82             int stCondFailures = xc->readStCondFailures();
  83             stCondFailures++;
  84             xc->setStCondFailures(stCondFailures);
  85             if (stCondFailures % 10 == 0) {
  86                 warn("%i: context %d: %d consecutive "
  87                      "store conditional failures\n",
  88                      curTick, xc->contextId(), stCondFailures);
  89             }
  90
  91             if (stCondFailures == 5000) {
  92                 panic("Max (5000) Store Conditional Fails Reached. Check Code For Deadlock.\n");
  93             }
  94
  95             if (!lock_flag){
  96                 DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, Store Conditional Failed.\n",
  97                         req->threadId());
  98             } else if ((req->getPaddr() & ~0xf) != lock_addr) {
  99                 DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, Store Conditional Failed.\n",
 100                         req->threadId());
 101             }
 102             // store conditional failed already, so don't issue it to mem
 103             return false;
 104         }
 105     }
 106
 107     return true;
 108 }
 109
 110
 111 } // namespace MipsISA
 112
 113 #endif