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34 * Authors: Steven K. Reinhardt
37 #ifndef __ARCH_MIPS_LOCKED_MEM_HH__
38 #define __ARCH_MIPS_LOCKED_MEM_HH__
43 * ISA-specific helper functions for locked memory accesses.
46 #include "arch/isa_traits.hh"
47 #include "base/misc.hh"
48 #include "base/trace.hh"
49 #include "mem/request.hh"
56 handleLockedRead(XC *xc, Request *req)
58 unsigned tid = req->getThreadNum();
59 xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf, tid);
60 xc->setMiscRegNoEffect(LLFlag, true, tid);
61 DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link Address set to %x.\n",
62 tid, req->getPaddr() & ~0xf);
68 handleLockedWrite(XC *xc, Request *req)
70 unsigned tid = req->getThreadNum();
72 if (req->isUncacheable()) {
73 // Funky Turbolaser mailbox access...don't update
74 // result register (see stq_c in decoder.isa)
77 // standard store conditional
78 bool lock_flag = xc->readMiscRegNoEffect(LLFlag, tid);
79 Addr lock_addr = xc->readMiscRegNoEffect(LLAddr, tid);
81 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
82 // Lock flag not set or addr mismatch in CPU;
83 // don't even bother sending to memory system
85 xc->setMiscRegNoEffect(LLFlag, false, tid);
87 // the rest of this code is not architectural;
88 // it's just a debugging aid to help detect
89 // livelock by warning on long sequences of failed
91 int stCondFailures = xc->readStCondFailures();
93 xc->setStCondFailures(stCondFailures);
94 if (stCondFailures % 10 == 0) {
95 warn("%i: cpu %d: %d consecutive "
96 "store conditional failures\n",
97 curTick, xc->readCpuId(), stCondFailures);
100 if (stCondFailures == 5000) {
101 panic("Max (5000) Store Conditional Fails Reached. Check Code For Deadlock.\n");
105 DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, Store Conditional Failed.\n",
107 } else if ((req->getPaddr() & ~0xf) != lock_addr) {
108 DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, Store Conditional Failed.\n",
111 // store conditional failed already, so don't issue it to mem
120 } // namespace MipsISA