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41 #ifndef __ARCH_MIPS_LOCKED_MEM_HH__
42 #define __ARCH_MIPS_LOCKED_MEM_HH__
47 * ISA-specific helper functions for locked memory accesses.
50 #include "arch/registers.hh"
51 #include "base/logging.hh"
52 #include "base/trace.hh"
53 #include "cpu/base.hh"
54 #include "debug/LLSC.hh"
55 #include "mem/packet.hh"
56 #include "mem/request.hh"
62 handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
64 if (!xc->readMiscReg(MISCREG_LLFLAG))
67 Addr locked_addr = xc->readMiscReg(MISCREG_LLADDR) & cacheBlockMask;
68 Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
70 if (locked_addr == snoop_addr)
71 xc->setMiscReg(MISCREG_LLFLAG, false);
77 handleLockedRead(XC *xc, const RequestPtr &req)
79 xc->setMiscReg(MISCREG_LLADDR, req->getPaddr() & ~0xf);
80 xc->setMiscReg(MISCREG_LLFLAG, true);
81 DPRINTF(LLSC, "[cid:%i]: Load-Link Flag Set & Load-Link"
82 " Address set to %x.\n",
83 req->contextId(), req->getPaddr() & ~0xf);
88 handleLockedSnoopHit(XC *xc)
94 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
96 if (req->isUncacheable()) {
97 // Funky Turbolaser mailbox access...don't update
98 // result register (see stq_c in decoder.isa)
101 // standard store conditional
102 bool lock_flag = xc->readMiscReg(MISCREG_LLFLAG);
103 Addr lock_addr = xc->readMiscReg(MISCREG_LLADDR);
105 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
106 // Lock flag not set or addr mismatch in CPU;
107 // don't even bother sending to memory system
108 req->setExtraData(0);
109 xc->setMiscReg(MISCREG_LLFLAG, false);
111 // the rest of this code is not architectural;
112 // it's just a debugging aid to help detect
113 // livelock by warning on long sequences of failed
114 // store conditionals
115 int stCondFailures = xc->readStCondFailures();
117 xc->setStCondFailures(stCondFailures);
118 if (stCondFailures % 100000 == 0) {
119 warn("%i: context %d: %d consecutive "
120 "store conditional failures\n",
121 curTick(), xc->contextId(), stCondFailures);
125 DPRINTF(LLSC, "[cid:%i]: Lock Flag Set, "
126 "Store Conditional Failed.\n",
128 } else if ((req->getPaddr() & ~0xf) != lock_addr) {
129 DPRINTF(LLSC, "[cid:%i]: Load-Link Address Mismatch, "
130 "Store Conditional Failed.\n",
133 // store conditional failed already, so don't issue it to mem
143 globalClearExclusive(XC *xc)
145 xc->getCpuPtr()->wakeup(xc->threadId());
148 } // namespace MipsISA