2 * Copyright (c) 2002, 2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
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9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Nathan Binkert
32 #include "arch/mips/faults.hh"
33 #include "arch/mips/isa_traits.hh"
34 #include "arch/mips/tlb.hh"
35 //#include "base/kgdb.h"
36 #include "base/remote_gdb.hh"
37 #include "base/stats/events.hh"
38 #include "config/full_system.hh"
39 #include "cpu/base.hh"
40 #include "cpu/simple_thread.hh"
41 #include "cpu/thread_context.hh"
42 #include "kern/kernel_stats.hh"
43 #include "sim/debug.hh"
44 #include "sim/sim_exit.hh"
45 #include "arch/mips/mips_core_specific.hh"
49 ////////////////////////////////////////////////////////////////////////
51 // Machine dependent functions
54 MipsISA::initCPU(ThreadContext
*tc
, int cpuId
)
57 // MipsFault *reset = new ResetFault;
58 // tc->setPC(reset->vect());
59 // tc->setNextPC(tc->readPC() + sizeof(MachInst));
66 MipsISA::processInterrupts(CPU
*cpu
)
68 //Check if there are any outstanding interrupts
69 //Handle the interrupts
73 cpu->checkInterrupts = false;
75 if (cpu->readMiscReg(IPR_ASTRR))
76 panic("asynchronous traps not implemented\n");
78 if (cpu->readMiscReg(IPR_SIRR)) {
79 for (int i = INTLEVEL_SOFTWARE_MIN;
80 i < INTLEVEL_SOFTWARE_MAX; i++) {
81 if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
82 // See table 4-19 of the 21164 hardware reference
83 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
84 summary |= (ULL(1) << i);
89 uint64_t interrupts = cpu->intr_status();
92 for (int i = INTLEVEL_EXTERNAL_MIN;
93 i < INTLEVEL_EXTERNAL_MAX; i++) {
94 if (interrupts & (ULL(1) << i)) {
95 // See table 4-19 of the 21164 hardware reference
97 summary |= (ULL(1) << i);
102 if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) {
103 cpu->setMiscReg(IPR_ISR, summary);
104 cpu->setMiscReg(IPR_INTID, ipl);
105 cpu->trap(new InterruptFault);
106 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
107 cpu->readMiscReg(IPR_IPLR), ipl, summary);
114 MipsISA::MiscRegFile::getInstAsid()
116 return AlphaISA::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
120 MipsISA::MiscRegFile::getDataAsid()
122 return AlphaISA::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
127 #endif // FULL_SYSTEM || BARE_IRON