src/arch/mips/mt.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  */
  30
  31 #ifndef __ARCH_MIPS_MT_HH__
  32 #define __ARCH_MIPS_MT_HH__
  33
  34 /**
  35  * @file
  36  *
  37  * ISA-specific helper functions for multithreaded execution.
  38  */
  39
  40 #include "arch/isa_traits.hh"
  41 #include "arch/mips/faults.hh"
  42 #include "arch/mips/mt_constants.hh"
  43 #include "base/bitfield.hh"
  44 #include "base/trace.hh"
  45 #include "base/misc.hh"
  46
  47 #include <iostream>
  48
  49 namespace MipsISA
  50 {
  51
  52
  53 template <class TC>
  54 inline unsigned
  55 getVirtProcNum(TC *tc)
  56 {
  57     MiscReg tcbind = tc->readMiscRegNoEffect(TCBind);
  58     return bits(tcbind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO);
  59 }
  60
  61 template <class TC>
  62 inline unsigned
  63 getTargetThread(TC *tc)
  64 {
  65     MiscReg vpec_ctrl = tc->readMiscRegNoEffect(VPEControl);
  66     return bits(vpec_ctrl, VPEC_TARG_TC_HI, VPEC_TARG_TC_LO);
  67 }
  68
  69 template <class TC>
  70 inline void
  71 haltThread(TC *tc)
  72 {
  73     if (tc->status() == TC::Active) {
  74         tc->halt();
  75
  76         // Save last known PC in TCRestart
  77         // @TODO: Needs to check if this is a branch and if so, take previous instruction
  78         tc->setMiscReg(TCRestart, tc->readNextPC());
  79
  80         warn("%i: Halting thread %i in %s @ PC %x, setting restart PC to %x", curTick, tc->threadId(), tc->getCpuPtr()->name(),
  81              tc->readPC(), tc->readNextPC());
  82     }
  83 }
  84
  85 template <class TC>
  86 inline void
  87 restoreThread(TC *tc)
  88 {
  89     if (tc->status() != TC::Active) {
  90         // Restore PC from TCRestart
  91         IntReg pc = tc->readMiscRegNoEffect(TCRestart);
  92
  93         // TODO: SET PC WITH AN EVENT INSTEAD OF INSTANTANEOUSLY
  94         // tc->setPCEvent(pc, pc + 4, pc + 8);
  95         tc->setPC(pc);
  96         tc->setNextPC(pc + 4);
  97         tc->setNextNPC(pc + 8);
  98         tc->activate(0);
  99
 100         warn("%i: Restoring thread %i in %s @ PC %x", curTick, tc->threadId(), tc->getCpuPtr()->name(),
 101              tc->readPC());
 102     }
 103 }
 104
 105 template <class TC>
 106 void
 107 forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
 108 {
 109     int num_threads = bits(tc->readMiscRegNoEffect(MVPConf0), MVPC0_PTC_HI, MVPC0_PTC_LO) + 1;
 110
 111     int success = 0;
 112     for (int tid = 0; tid < num_threads && success == 0; tid++) {
 113         unsigned tid_TCBind = tc->readRegOtherThread(MipsISA::TCBind + Ctrl_Base_DepTag,
 114                                                      tid);
 115         unsigned tc_bind = tc->readMiscRegNoEffect(MipsISA::TCBind);
 116
 117         if (bits(tid_TCBind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO) ==
 118             bits(tc_bind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO)) {
 119
 120             unsigned tid_TCStatus = tc->readRegOtherThread(MipsISA::TCStatus + Ctrl_Base_DepTag,
 121                                                            tid);
 122
 123             unsigned tid_TCHalt = tc->readRegOtherThread(MipsISA::TCHalt + Ctrl_Base_DepTag,
 124                                                          tid);
 125
 126             if (bits(tid_TCStatus, TCS_DA) == 1 &&
 127                 bits(tid_TCHalt, TCH_H) == 0    &&
 128                 bits(tid_TCStatus, TCS_A) == 0  &&
 129                 success == 0) {
 130
 131                 tc->setRegOtherThread(MipsISA::TCRestart + Ctrl_Base_DepTag, Rs, tid);
 132
 133                 tc->setRegOtherThread(Rd_bits, Rt, tid);
 134
 135                 unsigned status_ksu = bits(tc->readMiscReg(MipsISA::Status),
 136                                            S_KSU_HI, S_KSU_LO);
 137                 unsigned tc_status_asid = bits(tc->readMiscReg(MipsISA::TCStatus),
 138                                           TCS_ASID_HI, TCS_ASID_LO);
 139
 140                 // Set Run-State to Running
 141                 replaceBits(tid_TCStatus, TCSTATUS_RNST_HI, TCSTATUS_RNST_LO, 0);
 142
 143                 // Set Delay-Slot to 0
 144                 replaceBits(tid_TCStatus, TCSTATUS_TDS, 0);
 145
 146                 // Set Dirty TC to 1
 147                 replaceBits(tid_TCStatus, TCSTATUS_DT, 1);
 148
 149                 // Set Activated to 1
 150                 replaceBits(tid_TCStatus, TCSTATUS_A, 1);
 151
 152                 // Set status to previous thread's status
 153                 replaceBits(tid_TCStatus, TCSTATUS_TKSU_HI, TCSTATUS_TKSU_LO, status_ksu);
 154
 155                 // Set ASID to previous thread's state
 156                 replaceBits(tid_TCStatus, TCSTATUS_ASID_HI, TCSTATUS_ASID_LO, tc_status_asid);
 157
 158                 // Write Status Register
 159                 tc->setRegOtherThread(MipsISA::TCStatus + Ctrl_Base_DepTag,
 160                                       tid_TCStatus, tid);
 161
 162                 // Mark As Successful Fork
 163                 success = 1;
 164             }
 165         } else {
 166             std::cerr << "Bad VPEs" << std::endl;
 167         }
 168     }
 169
 170     if (success == 0) {
 171         unsigned vpe_control = tc->readMiscRegNoEffect(MipsISA::VPEControl);
 172         tc->setMiscReg(VPEControl, insertBits(vpe_control, VPEC_EXCPT_HI, VPEC_EXCPT_LO, 1));
 173         fault = new ThreadFault();
 174     }
 175 }
 176
 177
 178 template <class TC>
 179 int
 180 yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
 181 {
 182     if (src_reg == 0) {
 183         unsigned mvpconf0 = tc->readMiscRegNoEffect(MVPConf0);
 184         int num_threads = bits(mvpconf0, MVPC0_PTC_HI, MVPC0_PTC_LO) + 1;
 185
 186         int ok = 0;
 187
 188         // Get Current VPE & TC numbers from calling thread
 189         unsigned tcbind = tc->readMiscRegNoEffect(TCBind);
 190         unsigned cur_vpe = bits(tcbind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO);
 191         unsigned cur_tc = bits(tcbind, TCB_CUR_TC_HI, TCB_CUR_TC_LO);
 192
 193         for (int tid = 0; tid < num_threads; tid++) {
 194             unsigned tid_TCStatus = tc->readRegOtherThread(MipsISA::TCStatus + Ctrl_Base_DepTag,
 195                                                            tid);
 196             unsigned tid_TCHalt = tc->readRegOtherThread(MipsISA::TCHalt + Ctrl_Base_DepTag,
 197                                                          tid);
 198             unsigned tid_TCBind = tc->readRegOtherThread(MipsISA::TCBind + Ctrl_Base_DepTag,
 199                                                          tid);
 200
 201             unsigned tid_vpe = bits(tid_TCBind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO);
 202             unsigned tid_tc = bits(tid_TCBind, TCB_CUR_TC_HI, TCB_CUR_TC_LO);
 203             unsigned tid_tcstatus_da = bits(tid_TCStatus, TCS_DA);
 204             unsigned tid_tcstatus_a = bits(tid_TCStatus, TCS_A);
 205             unsigned tid_tchalt_h = bits(tid_TCHalt, TCH_H);
 206
 207             if (tid_vpe == cur_vpe &&
 208                 tid_tc == cur_tc &&
 209                 tid_tcstatus_da == 1 &&
 210                 tid_tchalt_h == 0    &&
 211                 tid_tcstatus_a == 1) {
 212                 ok = 1;
 213             }
 214         }
 215
 216         if (ok == 1) {
 217             unsigned tcstatus = tc->readMiscRegNoEffect(TCStatus);
 218             tc->setMiscReg(TCStatus, insertBits(tcstatus, TCS_A, TCS_A, 0));
 219             warn("%i: Deactivating Hardware Thread Context #%i", curTick, tc->threadId());
 220         }
 221     } else if (src_reg > 0) {
 222         if (src_reg && !yield_mask != 0) {
 223             unsigned vpe_control = tc->readMiscReg(VPEControl);
 224             tc->setMiscReg(VPEControl, insertBits(vpe_control, VPEC_EXCPT_HI, VPEC_EXCPT_LO, 2));
 225             fault = new ThreadFault();
 226         } else {
 227             //tc->setThreadRescheduleCondition(src_reg & yield_mask);
 228         }
 229     } else if (src_reg != -2) {
 230         unsigned tcstatus = tc->readMiscRegNoEffect(TCStatus);
 231         unsigned vpe_control = tc->readMiscRegNoEffect(VPEControl);
 232         unsigned tcstatus_dt = bits(tcstatus, TCS_DT);
 233         unsigned vpe_control_ysi = bits(vpe_control, VPEC_YSI);
 234
 235         if (vpe_control_ysi == 1 && tcstatus_dt == 1 ) {
 236             tc->setMiscReg(VPEControl, insertBits(vpe_control, VPEC_EXCPT_HI, VPEC_EXCPT_LO, 4));
 237             fault = new ThreadFault();
 238         } else {
 239             //tc->ScheduleOtherThreads();
 240             //std::cerr << "T" << tc->threadId() << "YIELD: Schedule Other Threads.\n" << std::endl;
 241             //tc->suspend();
 242             // Save last known PC in TCRestart
 243             // @TODO: Needs to check if this is a branch and if so, take previous instruction
 244             //tc->setMiscRegWithEffect(TCRestart, tc->readNextPC());
 245         }
 246     }
 247
 248     return src_reg & yield_mask;
 249 }
 250
 251
 252 // TC will usually be a object derived from ThreadContext
 253 // (src/cpu/thread_context.hh)
 254 template <class TC>
 255 inline void
 256 updateStatusView(TC *tc)
 257 {
 258     // TCStatus' register view must be the same as
 259     // Status register view for CU, MX, KSU bits
 260     MiscReg tc_status = tc->readMiscRegNoEffect(TCStatus);
 261     MiscReg status = tc->readMiscRegNoEffect(Status);
 262
 263     unsigned cu_bits = bits(tc_status, TCS_TCU_HI, TCS_TCU_LO);
 264     replaceBits(status, S_CU_HI, S_CU_LO, cu_bits);
 265
 266     unsigned mx_bits = bits(tc_status, TCS_TMX);
 267     replaceBits(status, S_MX, S_MX, mx_bits);
 268
 269     unsigned ksu_bits = bits(tc_status, TCS_TKSU_HI, TCS_TKSU_LO);
 270     replaceBits(status, S_KSU_HI, S_KSU_LO, ksu_bits);
 271
 272     tc->setMiscRegNoEffect(Status, status);
 273 }
 274
 275 // TC will usually be a object derived from ThreadContext
 276 // (src/cpu/thread_context.hh)
 277 template <class TC>
 278 inline void
 279 updateTCStatusView(TC *tc)
 280 {
 281     // TCStatus' register view must be the same as
 282     // Status register view for CU, MX, KSU bits
 283     MiscReg tc_status = tc->readMiscRegNoEffect(TCStatus);
 284     MiscReg status = tc->readMiscRegNoEffect(Status);
 285
 286     unsigned cu_bits = bits(status, S_CU_HI, S_CU_LO);
 287     replaceBits(tc_status, TCS_TCU_HI, TCS_TCU_LO, cu_bits);
 288
 289     unsigned mx_bits = bits(status, S_MX, S_MX);
 290     replaceBits(tc_status, TCS_TMX, mx_bits);
 291
 292     unsigned ksu_bits = bits(status, S_KSU_HI, S_KSU_LO);
 293     replaceBits(tc_status, TCS_TKSU_HI, TCS_TKSU_LO, ksu_bits);
 294
 295     tc->setMiscRegNoEffect(TCStatus, tc_status);
 296 }
 297
 298 } // namespace MipsISA
 299
 300
 301 #endif