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34 * Authors: Korey Sewell
39 #ifndef __ARCH_MIPS_MT_HH__
40 #define __ARCH_MIPS_MT_HH__
45 * ISA-specific helper functions for multithreaded execution.
48 #include "arch/isa_traits.hh"
49 #include "arch/mips/faults.hh"
50 #include "arch/mips/mt_constants.hh"
51 #include "base/bitfield.hh"
52 #include "base/trace.hh"
53 #include "base/misc.hh"
64 getVirtProcNum(TC *tc)
66 MiscReg tcbind = tc->readMiscRegNoEffect(TCBind);
67 return bits(tcbind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO);
72 getTargetThread(TC *tc)
74 MiscReg vpec_ctrl = tc->readMiscRegNoEffect(VPEControl);
75 return bits(vpec_ctrl, VPEC_TARG_TC_HI, VPEC_TARG_TC_LO);
82 if (tc->status() == TC::Active) {
85 // Save last known PC in TCRestart
86 // @TODO: Needs to check if this is a branch and if so, take previous instruction
87 tc->setMiscReg(TCRestart, tc->readNextPC());
89 warn("%i: Halting thread %i in %s @ PC %x, setting restart PC to %x", curTick, tc->getThreadNum(), tc->getCpuPtr()->name(),
90 tc->readPC(), tc->readNextPC());
98 if (tc->status() != TC::Active) {
99 // Restore PC from TCRestart
100 IntReg pc = tc->readMiscRegNoEffect(TCRestart);
102 // TODO: SET PC WITH AN EVENT INSTEAD OF INSTANTANEOUSLY
103 // tc->setPCEvent(pc, pc + 4, pc + 8);
105 tc->setNextPC(pc + 4);
106 tc->setNextNPC(pc + 8);
109 warn("%i: Restoring thread %i in %s @ PC %x", curTick, tc->getThreadNum(), tc->getCpuPtr()->name(),
116 forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
118 int num_threads = bits(tc->readMiscRegNoEffect(MVPConf0), MVPC0_PTC_HI, MVPC0_PTC_LO) + 1;
121 for (int tid = 0; tid < num_threads && success == 0; tid++) {
122 unsigned tid_TCBind = tc->readRegOtherThread(MipsISA::TCBind + Ctrl_Base_DepTag,
124 unsigned tc_bind = tc->readMiscRegNoEffect(MipsISA::TCBind);
126 if (bits(tid_TCBind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO) ==
127 bits(tc_bind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO)) {
129 unsigned tid_TCStatus = tc->readRegOtherThread(MipsISA::TCStatus + Ctrl_Base_DepTag,
132 unsigned tid_TCHalt = tc->readRegOtherThread(MipsISA::TCHalt + Ctrl_Base_DepTag,
135 if (bits(tid_TCStatus, TCS_DA) == 1 &&
136 bits(tid_TCHalt, TCH_H) == 0 &&
137 bits(tid_TCStatus, TCS_A) == 0 &&
140 tc->setRegOtherThread(MipsISA::TCRestart + Ctrl_Base_DepTag, Rs, tid);
142 tc->setRegOtherThread(Rd_bits, Rt, tid);
144 unsigned status_ksu = bits(tc->readMiscReg(MipsISA::Status),
146 unsigned tc_status_asid = bits(tc->readMiscReg(MipsISA::TCStatus),
147 TCS_ASID_HI, TCS_ASID_LO);
149 // Set Run-State to Running
150 replaceBits(tid_TCStatus, TCSTATUS_RNST_HI, TCSTATUS_RNST_LO, 0);
152 // Set Delay-Slot to 0
153 replaceBits(tid_TCStatus, TCSTATUS_TDS, 0);
156 replaceBits(tid_TCStatus, TCSTATUS_DT, 1);
158 // Set Activated to 1
159 replaceBits(tid_TCStatus, TCSTATUS_A, 1);
161 // Set status to previous thread's status
162 replaceBits(tid_TCStatus, TCSTATUS_TKSU_HI, TCSTATUS_TKSU_LO, status_ksu);
164 // Set ASID to previous thread's state
165 replaceBits(tid_TCStatus, TCSTATUS_ASID_HI, TCSTATUS_ASID_LO, tc_status_asid);
167 // Write Status Register
168 tc->setRegOtherThread(MipsISA::TCStatus + Ctrl_Base_DepTag,
171 // Mark As Successful Fork
175 std::cerr << "Bad VPEs" << endl;
180 unsigned vpe_control = tc->readMiscRegNoEffect(MipsISA::VPEControl);
181 tc->setMiscReg(VPEControl, insertBits(vpe_control, VPEC_EXCPT_HI, VPEC_EXCPT_LO, 1));
182 fault = new ThreadFault();
189 yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
192 unsigned mvpconf0 = tc->readMiscRegNoEffect(MVPConf0);
193 int num_threads = bits(mvpconf0, MVPC0_PTC_HI, MVPC0_PTC_LO) + 1;
197 // Get Current VPE & TC numbers from calling thread
198 unsigned tcbind = tc->readMiscRegNoEffect(TCBind);
199 unsigned cur_vpe = bits(tcbind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO);
200 unsigned cur_tc = bits(tcbind, TCB_CUR_TC_HI, TCB_CUR_TC_LO);
202 for (int tid = 0; tid < num_threads; tid++) {
203 unsigned tid_TCStatus = tc->readRegOtherThread(MipsISA::TCStatus + Ctrl_Base_DepTag,
205 unsigned tid_TCHalt = tc->readRegOtherThread(MipsISA::TCHalt + Ctrl_Base_DepTag,
207 unsigned tid_TCBind = tc->readRegOtherThread(MipsISA::TCBind + Ctrl_Base_DepTag,
210 unsigned tid_vpe = bits(tid_TCBind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO);
211 unsigned tid_tc = bits(tid_TCBind, TCB_CUR_TC_HI, TCB_CUR_TC_LO);
212 unsigned tid_tcstatus_da = bits(tid_TCStatus, TCS_DA);
213 unsigned tid_tcstatus_a = bits(tid_TCStatus, TCS_A);
214 unsigned tid_tchalt_h = bits(tid_TCHalt, TCH_H);
216 if (tid_vpe == cur_vpe &&
218 tid_tcstatus_da == 1 &&
220 tid_tcstatus_a == 1) {
226 unsigned tcstatus = tc->readMiscRegNoEffect(TCStatus);
227 tc->setMiscReg(TCStatus, insertBits(tcstatus, TCS_A, TCS_A, 0));
228 warn("%i: Deactivating Hardware Thread Context #%i", curTick, tc->getThreadNum());
230 } else if (src_reg > 0) {
231 if (src_reg & !yield_mask != 0) {
232 unsigned vpe_control = tc->readMiscReg(VPEControl);
233 tc->setMiscReg(VPEControl, insertBits(vpe_control, VPEC_EXCPT_HI, VPEC_EXCPT_LO, 2));
234 fault = new ThreadFault();
236 //tc->setThreadRescheduleCondition(src_reg & yield_mask);
238 } else if (src_reg != -2) {
239 unsigned tcstatus = tc->readMiscRegNoEffect(TCStatus);
240 unsigned vpe_control = tc->readMiscRegNoEffect(VPEControl);
241 unsigned tcstatus_dt = bits(tcstatus, TCS_DT);
242 unsigned vpe_control_ysi = bits(vpe_control, VPEC_YSI);
244 if (vpe_control_ysi == 1 && tcstatus_dt == 1 ) {
245 tc->setMiscReg(VPEControl, insertBits(vpe_control, VPEC_EXCPT_HI, VPEC_EXCPT_LO, 4));
246 fault = new ThreadFault();
248 //tc->ScheduleOtherThreads();
249 //std::cerr << "T" << tc->getThreadNum() << "YIELD: Schedule Other Threads.\n" << std::endl;
251 // Save last known PC in TCRestart
252 // @TODO: Needs to check if this is a branch and if so, take previous instruction
253 //tc->setMiscRegWithEffect(TCRestart, tc->readNextPC());
257 return src_reg & yield_mask;
261 // TC will usually be a object derived from ThreadContext
262 // (src/cpu/thread_context.hh)
265 updateStatusView(TC *tc)
267 // TCStatus' register view must be the same as
268 // Status register view for CU, MX, KSU bits
269 MiscReg tc_status = tc->readMiscRegNoEffect(TCStatus);
270 MiscReg status = tc->readMiscRegNoEffect(Status);
272 unsigned cu_bits = bits(tc_status, TCS_TCU_HI, TCS_TCU_LO);
273 replaceBits(status, S_CU_HI, S_CU_LO, cu_bits);
275 unsigned mx_bits = bits(tc_status, TCS_TMX);
276 replaceBits(status, S_MX, S_MX, mx_bits);
278 unsigned ksu_bits = bits(tc_status, TCS_TKSU_HI, TCS_TKSU_LO);
279 replaceBits(status, S_KSU_HI, S_KSU_LO, ksu_bits);
281 tc->setMiscRegNoEffect(Status, status);
284 // TC will usually be a object derived from ThreadContext
285 // (src/cpu/thread_context.hh)
288 updateTCStatusView(TC *tc)
290 // TCStatus' register view must be the same as
291 // Status register view for CU, MX, KSU bits
292 MiscReg tc_status = tc->readMiscRegNoEffect(TCStatus);
293 MiscReg status = tc->readMiscRegNoEffect(Status);
295 unsigned cu_bits = bits(status, S_CU_HI, S_CU_LO);
296 replaceBits(tc_status, TCS_TCU_HI, TCS_TCU_LO, cu_bits);
298 unsigned mx_bits = bits(status, S_MX, S_MX);
299 replaceBits(tc_status, TCS_TMX, mx_bits);
301 unsigned ksu_bits = bits(status, S_KSU_HI, S_KSU_LO);
302 replaceBits(tc_status, TCS_TKSU_HI, TCS_TKSU_LO, ksu_bits);
304 tc->setMiscRegNoEffect(TCStatus, tc_status);
307 } // namespace MipsISA