2 * Copyright (c) 2007 MIPS Technologies, Inc.
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16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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28 * Authors: Korey Sewell
31 #ifndef __ARCH_MIPS_MT_HH__
32 #define __ARCH_MIPS_MT_HH__
37 * ISA-specific helper functions for multithreaded execution.
40 #include "arch/isa_traits.hh"
41 #include "arch/mips/faults.hh"
42 #include "arch/mips/mt_constants.hh"
43 #include "base/bitfield.hh"
44 #include "base/trace.hh"
45 #include "base/misc.hh"
55 getVirtProcNum(TC *tc)
57 MiscReg tcbind = tc->readMiscRegNoEffect(TCBind);
58 return bits(tcbind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO);
63 getTargetThread(TC *tc)
65 MiscReg vpec_ctrl = tc->readMiscRegNoEffect(VPEControl);
66 return bits(vpec_ctrl, VPEC_TARG_TC_HI, VPEC_TARG_TC_LO);
73 if (tc->status() == TC::Active) {
76 // Save last known PC in TCRestart
77 // @TODO: Needs to check if this is a branch and if so, take previous instruction
78 tc->setMiscReg(TCRestart, tc->readNextPC());
80 warn("%i: Halting thread %i in %s @ PC %x, setting restart PC to %x", curTick, tc->threadId(), tc->getCpuPtr()->name(),
81 tc->readPC(), tc->readNextPC());
89 if (tc->status() != TC::Active) {
90 // Restore PC from TCRestart
91 IntReg pc = tc->readMiscRegNoEffect(TCRestart);
93 // TODO: SET PC WITH AN EVENT INSTEAD OF INSTANTANEOUSLY
94 // tc->setPCEvent(pc, pc + 4, pc + 8);
96 tc->setNextPC(pc + 4);
97 tc->setNextNPC(pc + 8);
100 warn("%i: Restoring thread %i in %s @ PC %x", curTick, tc->threadId(), tc->getCpuPtr()->name(),
107 forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
109 int num_threads = bits(tc->readMiscRegNoEffect(MVPConf0), MVPC0_PTC_HI, MVPC0_PTC_LO) + 1;
112 for (ThreadID tid = 0; tid < num_threads && success == 0; tid++) {
113 unsigned tid_TCBind = tc->readRegOtherThread(MipsISA::TCBind + Ctrl_Base_DepTag,
115 unsigned tc_bind = tc->readMiscRegNoEffect(MipsISA::TCBind);
117 if (bits(tid_TCBind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO) ==
118 bits(tc_bind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO)) {
120 unsigned tid_TCStatus = tc->readRegOtherThread(MipsISA::TCStatus + Ctrl_Base_DepTag,
123 unsigned tid_TCHalt = tc->readRegOtherThread(MipsISA::TCHalt + Ctrl_Base_DepTag,
126 if (bits(tid_TCStatus, TCS_DA) == 1 &&
127 bits(tid_TCHalt, TCH_H) == 0 &&
128 bits(tid_TCStatus, TCS_A) == 0 &&
131 tc->setRegOtherThread(MipsISA::TCRestart + Ctrl_Base_DepTag, Rs, tid);
133 tc->setRegOtherThread(Rd_bits, Rt, tid);
135 unsigned status_ksu = bits(tc->readMiscReg(MipsISA::Status),
137 unsigned tc_status_asid = bits(tc->readMiscReg(MipsISA::TCStatus),
138 TCS_ASID_HI, TCS_ASID_LO);
140 // Set Run-State to Running
141 replaceBits(tid_TCStatus, TCSTATUS_RNST_HI, TCSTATUS_RNST_LO, 0);
143 // Set Delay-Slot to 0
144 replaceBits(tid_TCStatus, TCSTATUS_TDS, 0);
147 replaceBits(tid_TCStatus, TCSTATUS_DT, 1);
149 // Set Activated to 1
150 replaceBits(tid_TCStatus, TCSTATUS_A, 1);
152 // Set status to previous thread's status
153 replaceBits(tid_TCStatus, TCSTATUS_TKSU_HI, TCSTATUS_TKSU_LO, status_ksu);
155 // Set ASID to previous thread's state
156 replaceBits(tid_TCStatus, TCSTATUS_ASID_HI, TCSTATUS_ASID_LO, tc_status_asid);
158 // Write Status Register
159 tc->setRegOtherThread(MipsISA::TCStatus + Ctrl_Base_DepTag,
162 // Mark As Successful Fork
166 std::cerr << "Bad VPEs" << std::endl;
171 unsigned vpe_control = tc->readMiscRegNoEffect(MipsISA::VPEControl);
172 tc->setMiscReg(VPEControl, insertBits(vpe_control, VPEC_EXCPT_HI, VPEC_EXCPT_LO, 1));
173 fault = new ThreadFault();
180 yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
183 unsigned mvpconf0 = tc->readMiscRegNoEffect(MVPConf0);
184 ThreadID num_threads = bits(mvpconf0, MVPC0_PTC_HI, MVPC0_PTC_LO) + 1;
188 // Get Current VPE & TC numbers from calling thread
189 unsigned tcbind = tc->readMiscRegNoEffect(TCBind);
190 unsigned cur_vpe = bits(tcbind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO);
191 unsigned cur_tc = bits(tcbind, TCB_CUR_TC_HI, TCB_CUR_TC_LO);
193 for (ThreadID tid = 0; tid < num_threads; tid++) {
194 unsigned tid_TCStatus = tc->readRegOtherThread(MipsISA::TCStatus + Ctrl_Base_DepTag,
196 unsigned tid_TCHalt = tc->readRegOtherThread(MipsISA::TCHalt + Ctrl_Base_DepTag,
198 unsigned tid_TCBind = tc->readRegOtherThread(MipsISA::TCBind + Ctrl_Base_DepTag,
201 unsigned tid_vpe = bits(tid_TCBind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO);
202 unsigned tid_tc = bits(tid_TCBind, TCB_CUR_TC_HI, TCB_CUR_TC_LO);
203 unsigned tid_tcstatus_da = bits(tid_TCStatus, TCS_DA);
204 unsigned tid_tcstatus_a = bits(tid_TCStatus, TCS_A);
205 unsigned tid_tchalt_h = bits(tid_TCHalt, TCH_H);
207 if (tid_vpe == cur_vpe &&
209 tid_tcstatus_da == 1 &&
211 tid_tcstatus_a == 1) {
217 unsigned tcstatus = tc->readMiscRegNoEffect(TCStatus);
218 tc->setMiscReg(TCStatus, insertBits(tcstatus, TCS_A, TCS_A, 0));
219 warn("%i: Deactivating Hardware Thread Context #%i", curTick, tc->threadId());
221 } else if (src_reg > 0) {
222 if (src_reg && !yield_mask != 0) {
223 unsigned vpe_control = tc->readMiscReg(VPEControl);
224 tc->setMiscReg(VPEControl, insertBits(vpe_control, VPEC_EXCPT_HI, VPEC_EXCPT_LO, 2));
225 fault = new ThreadFault();
227 //tc->setThreadRescheduleCondition(src_reg & yield_mask);
229 } else if (src_reg != -2) {
230 unsigned tcstatus = tc->readMiscRegNoEffect(TCStatus);
231 unsigned vpe_control = tc->readMiscRegNoEffect(VPEControl);
232 unsigned tcstatus_dt = bits(tcstatus, TCS_DT);
233 unsigned vpe_control_ysi = bits(vpe_control, VPEC_YSI);
235 if (vpe_control_ysi == 1 && tcstatus_dt == 1 ) {
236 tc->setMiscReg(VPEControl, insertBits(vpe_control, VPEC_EXCPT_HI, VPEC_EXCPT_LO, 4));
237 fault = new ThreadFault();
239 //tc->ScheduleOtherThreads();
240 //std::cerr << "T" << tc->threadId() << "YIELD: Schedule Other Threads.\n" << std::endl;
242 // Save last known PC in TCRestart
243 // @TODO: Needs to check if this is a branch and if so, take previous instruction
244 //tc->setMiscRegWithEffect(TCRestart, tc->readNextPC());
248 return src_reg & yield_mask;
252 // TC will usually be a object derived from ThreadContext
253 // (src/cpu/thread_context.hh)
256 updateStatusView(TC *tc)
258 // TCStatus' register view must be the same as
259 // Status register view for CU, MX, KSU bits
260 MiscReg tc_status = tc->readMiscRegNoEffect(TCStatus);
261 MiscReg status = tc->readMiscRegNoEffect(Status);
263 unsigned cu_bits = bits(tc_status, TCS_TCU_HI, TCS_TCU_LO);
264 replaceBits(status, S_CU_HI, S_CU_LO, cu_bits);
266 unsigned mx_bits = bits(tc_status, TCS_TMX);
267 replaceBits(status, S_MX, S_MX, mx_bits);
269 unsigned ksu_bits = bits(tc_status, TCS_TKSU_HI, TCS_TKSU_LO);
270 replaceBits(status, S_KSU_HI, S_KSU_LO, ksu_bits);
272 tc->setMiscRegNoEffect(Status, status);
275 // TC will usually be a object derived from ThreadContext
276 // (src/cpu/thread_context.hh)
279 updateTCStatusView(TC *tc)
281 // TCStatus' register view must be the same as
282 // Status register view for CU, MX, KSU bits
283 MiscReg tc_status = tc->readMiscRegNoEffect(TCStatus);
284 MiscReg status = tc->readMiscRegNoEffect(Status);
286 unsigned cu_bits = bits(status, S_CU_HI, S_CU_LO);
287 replaceBits(tc_status, TCS_TCU_HI, TCS_TCU_LO, cu_bits);
289 unsigned mx_bits = bits(status, S_MX, S_MX);
290 replaceBits(tc_status, TCS_TMX, mx_bits);
292 unsigned ksu_bits = bits(status, S_KSU_HI, S_KSU_LO);
293 replaceBits(tc_status, TCS_TKSU_HI, TCS_TKSU_LO, ksu_bits);
295 tc->setMiscRegNoEffect(TCStatus, tc_status);
298 } // namespace MipsISA