2 * Copyright (c) 2007 MIPS Technologies, Inc.
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16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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28 * Authors: Korey Sewell
31 #ifndef __ARCH_MIPS_MT_HH__
32 #define __ARCH_MIPS_MT_HH__
37 * ISA-specific helper functions for multithreaded execution.
40 #include "arch/mips/faults.hh"
41 #include "arch/mips/isa_traits.hh"
42 #include "arch/mips/mt_constants.hh"
43 #include "arch/mips/registers.hh"
44 #include "base/bitfield.hh"
45 #include "base/trace.hh"
46 #include "base/misc.hh"
56 getVirtProcNum(TC *tc)
58 MiscReg tcbind = tc->readMiscRegNoEffect(TCBind);
59 return bits(tcbind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO);
64 getTargetThread(TC *tc)
66 MiscReg vpec_ctrl = tc->readMiscRegNoEffect(VPEControl);
67 return bits(vpec_ctrl, VPEC_TARG_TC_HI, VPEC_TARG_TC_LO);
74 if (tc->status() == TC::Active) {
77 // Save last known PC in TCRestart
78 // @TODO: Needs to check if this is a branch and if so, take previous instruction
79 tc->setMiscReg(TCRestart, tc->readNextPC());
81 warn("%i: Halting thread %i in %s @ PC %x, setting restart PC to %x", curTick, tc->threadId(), tc->getCpuPtr()->name(),
82 tc->readPC(), tc->readNextPC());
90 if (tc->status() != TC::Active) {
91 // Restore PC from TCRestart
92 IntReg pc = tc->readMiscRegNoEffect(TCRestart);
94 // TODO: SET PC WITH AN EVENT INSTEAD OF INSTANTANEOUSLY
95 // tc->setPCEvent(pc, pc + 4, pc + 8);
97 tc->setNextPC(pc + 4);
98 tc->setNextNPC(pc + 8);
101 warn("%i: Restoring thread %i in %s @ PC %x", curTick, tc->threadId(), tc->getCpuPtr()->name(),
108 forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
110 int num_threads = bits(tc->readMiscRegNoEffect(MVPConf0), MVPC0_PTC_HI, MVPC0_PTC_LO) + 1;
113 for (ThreadID tid = 0; tid < num_threads && success == 0; tid++) {
114 unsigned tid_TCBind = tc->readRegOtherThread(MipsISA::TCBind + Ctrl_Base_DepTag,
116 unsigned tc_bind = tc->readMiscRegNoEffect(MipsISA::TCBind);
118 if (bits(tid_TCBind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO) ==
119 bits(tc_bind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO)) {
121 unsigned tid_TCStatus = tc->readRegOtherThread(MipsISA::TCStatus + Ctrl_Base_DepTag,
124 unsigned tid_TCHalt = tc->readRegOtherThread(MipsISA::TCHalt + Ctrl_Base_DepTag,
127 if (bits(tid_TCStatus, TCS_DA) == 1 &&
128 bits(tid_TCHalt, TCH_H) == 0 &&
129 bits(tid_TCStatus, TCS_A) == 0 &&
132 tc->setRegOtherThread(MipsISA::TCRestart + Ctrl_Base_DepTag, Rs, tid);
134 tc->setRegOtherThread(Rd_bits, Rt, tid);
136 unsigned status_ksu = bits(tc->readMiscReg(MipsISA::Status),
138 unsigned tc_status_asid = bits(tc->readMiscReg(MipsISA::TCStatus),
139 TCS_ASID_HI, TCS_ASID_LO);
141 // Set Run-State to Running
142 replaceBits(tid_TCStatus, TCSTATUS_RNST_HI, TCSTATUS_RNST_LO, 0);
144 // Set Delay-Slot to 0
145 replaceBits(tid_TCStatus, TCSTATUS_TDS, 0);
148 replaceBits(tid_TCStatus, TCSTATUS_DT, 1);
150 // Set Activated to 1
151 replaceBits(tid_TCStatus, TCSTATUS_A, 1);
153 // Set status to previous thread's status
154 replaceBits(tid_TCStatus, TCSTATUS_TKSU_HI, TCSTATUS_TKSU_LO, status_ksu);
156 // Set ASID to previous thread's state
157 replaceBits(tid_TCStatus, TCSTATUS_ASID_HI, TCSTATUS_ASID_LO, tc_status_asid);
159 // Write Status Register
160 tc->setRegOtherThread(MipsISA::TCStatus + Ctrl_Base_DepTag,
163 // Mark As Successful Fork
167 std::cerr << "Bad VPEs" << std::endl;
172 unsigned vpe_control = tc->readMiscRegNoEffect(MipsISA::VPEControl);
173 tc->setMiscReg(VPEControl, insertBits(vpe_control, VPEC_EXCPT_HI, VPEC_EXCPT_LO, 1));
174 fault = new ThreadFault();
181 yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
184 unsigned mvpconf0 = tc->readMiscRegNoEffect(MVPConf0);
185 ThreadID num_threads = bits(mvpconf0, MVPC0_PTC_HI, MVPC0_PTC_LO) + 1;
189 // Get Current VPE & TC numbers from calling thread
190 unsigned tcbind = tc->readMiscRegNoEffect(TCBind);
191 unsigned cur_vpe = bits(tcbind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO);
192 unsigned cur_tc = bits(tcbind, TCB_CUR_TC_HI, TCB_CUR_TC_LO);
194 for (ThreadID tid = 0; tid < num_threads; tid++) {
195 unsigned tid_TCStatus = tc->readRegOtherThread(MipsISA::TCStatus + Ctrl_Base_DepTag,
197 unsigned tid_TCHalt = tc->readRegOtherThread(MipsISA::TCHalt + Ctrl_Base_DepTag,
199 unsigned tid_TCBind = tc->readRegOtherThread(MipsISA::TCBind + Ctrl_Base_DepTag,
202 unsigned tid_vpe = bits(tid_TCBind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO);
203 unsigned tid_tc = bits(tid_TCBind, TCB_CUR_TC_HI, TCB_CUR_TC_LO);
204 unsigned tid_tcstatus_da = bits(tid_TCStatus, TCS_DA);
205 unsigned tid_tcstatus_a = bits(tid_TCStatus, TCS_A);
206 unsigned tid_tchalt_h = bits(tid_TCHalt, TCH_H);
208 if (tid_vpe == cur_vpe &&
210 tid_tcstatus_da == 1 &&
212 tid_tcstatus_a == 1) {
218 unsigned tcstatus = tc->readMiscRegNoEffect(TCStatus);
219 tc->setMiscReg(TCStatus, insertBits(tcstatus, TCS_A, TCS_A, 0));
220 warn("%i: Deactivating Hardware Thread Context #%i", curTick, tc->threadId());
222 } else if (src_reg > 0) {
223 if (src_reg && !yield_mask != 0) {
224 unsigned vpe_control = tc->readMiscReg(VPEControl);
225 tc->setMiscReg(VPEControl, insertBits(vpe_control, VPEC_EXCPT_HI, VPEC_EXCPT_LO, 2));
226 fault = new ThreadFault();
228 //tc->setThreadRescheduleCondition(src_reg & yield_mask);
230 } else if (src_reg != -2) {
231 unsigned tcstatus = tc->readMiscRegNoEffect(TCStatus);
232 unsigned vpe_control = tc->readMiscRegNoEffect(VPEControl);
233 unsigned tcstatus_dt = bits(tcstatus, TCS_DT);
234 unsigned vpe_control_ysi = bits(vpe_control, VPEC_YSI);
236 if (vpe_control_ysi == 1 && tcstatus_dt == 1 ) {
237 tc->setMiscReg(VPEControl, insertBits(vpe_control, VPEC_EXCPT_HI, VPEC_EXCPT_LO, 4));
238 fault = new ThreadFault();
240 //tc->ScheduleOtherThreads();
241 //std::cerr << "T" << tc->threadId() << "YIELD: Schedule Other Threads.\n" << std::endl;
243 // Save last known PC in TCRestart
244 // @TODO: Needs to check if this is a branch and if so, take previous instruction
245 //tc->setMiscRegWithEffect(TCRestart, tc->readNextPC());
249 return src_reg & yield_mask;
253 // TC will usually be a object derived from ThreadContext
254 // (src/cpu/thread_context.hh)
257 updateStatusView(TC *tc)
259 // TCStatus' register view must be the same as
260 // Status register view for CU, MX, KSU bits
261 MiscReg tc_status = tc->readMiscRegNoEffect(TCStatus);
262 MiscReg status = tc->readMiscRegNoEffect(Status);
264 unsigned cu_bits = bits(tc_status, TCS_TCU_HI, TCS_TCU_LO);
265 replaceBits(status, S_CU_HI, S_CU_LO, cu_bits);
267 unsigned mx_bits = bits(tc_status, TCS_TMX);
268 replaceBits(status, S_MX, S_MX, mx_bits);
270 unsigned ksu_bits = bits(tc_status, TCS_TKSU_HI, TCS_TKSU_LO);
271 replaceBits(status, S_KSU_HI, S_KSU_LO, ksu_bits);
273 tc->setMiscRegNoEffect(Status, status);
276 // TC will usually be a object derived from ThreadContext
277 // (src/cpu/thread_context.hh)
280 updateTCStatusView(TC *tc)
282 // TCStatus' register view must be the same as
283 // Status register view for CU, MX, KSU bits
284 MiscReg tc_status = tc->readMiscRegNoEffect(TCStatus);
285 MiscReg status = tc->readMiscRegNoEffect(Status);
287 unsigned cu_bits = bits(status, S_CU_HI, S_CU_LO);
288 replaceBits(tc_status, TCS_TCU_HI, TCS_TCU_LO, cu_bits);
290 unsigned mx_bits = bits(status, S_MX, S_MX);
291 replaceBits(tc_status, TCS_TMX, mx_bits);
293 unsigned ksu_bits = bits(status, S_KSU_HI, S_KSU_LO);
294 replaceBits(tc_status, TCS_TKSU_HI, TCS_TKSU_LO, ksu_bits);
296 tc->setMiscRegNoEffect(TCStatus, tc_status);
299 } // namespace MipsISA