src/arch/mips/mt.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  */
  30
  31 #ifndef __ARCH_MIPS_MT_HH__
  32 #define __ARCH_MIPS_MT_HH__
  33
  34 /**
  35  * @file
  36  *
  37  * ISA-specific helper functions for multithreaded execution.
  38  */
  39
  40 #include "arch/mips/faults.hh"
  41 #include "arch/mips/isa_traits.hh"
  42 #include "arch/mips/mt_constants.hh"
  43 #include "arch/mips/pra_constants.hh"
  44 #include "arch/mips/registers.hh"
  45 #include "base/bitfield.hh"
  46 #include "base/trace.hh"
  47 #include "base/misc.hh"
  48
  49 #include <iostream>
  50
  51 namespace MipsISA
  52 {
  53
  54 template <class TC>
  55 inline unsigned
  56 getVirtProcNum(TC *tc)
  57 {
  58     TCBindReg tcbind = tc->readMiscRegNoEffect(TCBind);
  59     return tcbind.curVPE;
  60 }
  61
  62 template <class TC>
  63 inline unsigned
  64 getTargetThread(TC *tc)
  65 {
  66     VPEControlReg vpeCtrl = tc->readMiscRegNoEffect(VPEControl);
  67     return vpeCtrl.targTC;
  68 }
  69
  70 template <class TC>
  71 inline void
  72 haltThread(TC *tc)
  73 {
  74     if (tc->status() == TC::Active) {
  75         tc->halt();
  76
  77         // Save last known PC in TCRestart
  78         // @TODO: Needs to check if this is a branch and if so,
  79         // take previous instruction
  80         tc->setMiscReg(TCRestart, tc->readNextPC());
  81
  82         warn("%i: Halting thread %i in %s @ PC %x, setting restart PC to %x",
  83                 curTick, tc->threadId(), tc->getCpuPtr()->name(),
  84                 tc->readPC(), tc->readNextPC());
  85     }
  86 }
  87
  88 template <class TC>
  89 inline void
  90 restoreThread(TC *tc)
  91 {
  92     if (tc->status() != TC::Active) {
  93         // Restore PC from TCRestart
  94         IntReg pc = tc->readMiscRegNoEffect(TCRestart);
  95
  96         // TODO: SET PC WITH AN EVENT INSTEAD OF INSTANTANEOUSLY
  97         tc->setPC(pc);
  98         tc->setNextPC(pc + 4);
  99         tc->setNextNPC(pc + 8);
 100         tc->activate(0);
 101
 102         warn("%i: Restoring thread %i in %s @ PC %x",
 103                 curTick, tc->threadId(), tc->getCpuPtr()->name(),
 104                 tc->readPC());
 105     }
 106 }
 107
 108 template <class TC>
 109 void
 110 forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
 111 {
 112     MVPConf0Reg mvpConf = tc->readMiscRegNoEffect(MVPConf0);
 113     int num_threads = mvpConf.ptc + 1;
 114
 115     int success = 0;
 116     for (ThreadID tid = 0; tid < num_threads && success == 0; tid++) {
 117         TCBindReg tidTCBind =
 118             tc->readRegOtherThread(TCBind + Ctrl_Base_DepTag, tid);
 119         TCBindReg tcBind = tc->readMiscRegNoEffect(TCBind);
 120
 121         if (tidTCBind.curVPE = tcBind.curVPE) {
 122
 123             TCStatusReg tidTCStatus =
 124                 tc->readRegOtherThread(TCStatus + Ctrl_Base_DepTag,tid);
 125
 126             TCHaltReg tidTCHalt =
 127                 tc->readRegOtherThread(TCHalt + Ctrl_Base_DepTag,tid);
 128
 129             if (tidTCStatus.da == 1 && tidTCHalt.h == 0 &&
 130                 tidTCStatus.a == 0 && success == 0) {
 131
 132                 tc->setRegOtherThread(TCRestart + Ctrl_Base_DepTag, Rs, tid);
 133                 tc->setRegOtherThread(Rd_bits, Rt, tid);
 134
 135                 StatusReg status = tc->readMiscReg(Status);
 136                 TCStatusReg tcStatus = tc->readMiscReg(TCStatus);
 137
 138                 // Set Run-State to Running
 139                 tidTCStatus.rnst = 0;
 140                 // Set Delay-Slot to 0
 141                 tidTCStatus.tds = 0;
 142                 // Set Dirty TC to 1
 143                 tidTCStatus.dt = 1;
 144                 // Set Activated to 1
 145                 tidTCStatus.a = 1;
 146                 // Set status to previous thread's status
 147                 tidTCStatus.tksu = status.ksu;
 148                 // Set ASID to previous thread's state
 149                 tidTCStatus.asid = tcStatus.asid;
 150
 151                 // Write Status Register
 152                 tc->setRegOtherThread(TCStatus + Ctrl_Base_DepTag,
 153                                       tidTCStatus, tid);
 154
 155                 // Mark As Successful Fork
 156                 success = 1;
 157             }
 158         } else {
 159             std::cerr << "Bad VPEs" << std::endl;
 160         }
 161     }
 162
 163     if (success == 0) {
 164         VPEControlReg vpeControl = tc->readMiscRegNoEffect(VPEControl);
 165         vpeControl.excpt = 1;
 166         tc->setMiscReg(VPEControl, vpeControl);
 167         fault = new ThreadFault();
 168     }
 169 }
 170
 171
 172 template <class TC>
 173 int
 174 yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
 175 {
 176     if (src_reg == 0) {
 177         MVPConf0Reg mvpConf0 = tc->readMiscRegNoEffect(MVPConf0);
 178         ThreadID num_threads = mvpConf0.ptc + 1;
 179
 180         int ok = 0;
 181
 182         // Get Current VPE & TC numbers from calling thread
 183         TCBindReg tcBind = tc->readMiscRegNoEffect(TCBind);
 184
 185         for (ThreadID tid = 0; tid < num_threads; tid++) {
 186             TCStatusReg tidTCStatus =
 187                 tc->readRegOtherThread(TCStatus + Ctrl_Base_DepTag, tid);
 188             TCHaltReg tidTCHalt =
 189                 tc->readRegOtherThread(TCHalt + Ctrl_Base_DepTag, tid);
 190             TCBindReg tidTCBind =
 191                 tc->readRegOtherThread(TCBind + Ctrl_Base_DepTag, tid);
 192
 193             if (tidTCBind.curVPE == tcBind.curVPE &&
 194                 tidTCBind.curTC == tcBind.curTC &&
 195                 tidTCStatus.da == 1 &&
 196                 tidTCHalt.h == 0    &&
 197                 tidTCStatus.a == 1) {
 198                 ok = 1;
 199             }
 200         }
 201
 202         if (ok == 1) {
 203             TCStatusReg tcStatus = tc->readMiscRegNoEffect(TCStatus);
 204             tcStatus.a = 0;
 205             tc->setMiscReg(TCStatus, tcStatus);
 206             warn("%i: Deactivating Hardware Thread Context #%i",
 207                     curTick, tc->threadId());
 208         }
 209     } else if (src_reg > 0) {
 210         if (src_reg && !yield_mask != 0) {
 211             VPEControlReg vpeControl = tc->readMiscReg(VPEControl);
 212             vpeControl.excpt = 2;
 213             tc->setMiscReg(VPEControl, vpeControl);
 214             fault = new ThreadFault();
 215         } else {
 216         }
 217     } else if (src_reg != -2) {
 218         TCStatusReg tcStatus = tc->readMiscRegNoEffect(TCStatus);
 219         VPEControlReg vpeControl = tc->readMiscRegNoEffect(VPEControl);
 220
 221         if (vpeControl.ysi == 1 && tcStatus.dt == 1 ) {
 222             vpeControl.excpt = 4;
 223             fault = new ThreadFault();
 224         } else {
 225         }
 226     }
 227
 228     return src_reg & yield_mask;
 229 }
 230
 231
 232 // TC will usually be a object derived from ThreadContext
 233 // (src/cpu/thread_context.hh)
 234 template <class TC>
 235 inline void
 236 updateStatusView(TC *tc)
 237 {
 238     // TCStatus' register view must be the same as
 239     // Status register view for CU, MX, KSU bits
 240     TCStatusReg tcStatus = tc->readMiscRegNoEffect(TCStatus);
 241     StatusReg status = tc->readMiscRegNoEffect(Status);
 242
 243     status.cu = tcStatus.tcu;
 244     status.mx = tcStatus.tmx;
 245     status.ksu = tcStatus.tksu;
 246
 247     tc->setMiscRegNoEffect(Status, status);
 248 }
 249
 250 // TC will usually be a object derived from ThreadContext
 251 // (src/cpu/thread_context.hh)
 252 template <class TC>
 253 inline void
 254 updateTCStatusView(TC *tc)
 255 {
 256     // TCStatus' register view must be the same as
 257     // Status register view for CU, MX, KSU bits
 258     TCStatusReg tcStatus = tc->readMiscRegNoEffect(TCStatus);
 259     StatusReg status = tc->readMiscRegNoEffect(Status);
 260
 261     tcStatus.tcu = status.cu;
 262     tcStatus.tmx = status.mx;
 263     tcStatus.tksu = status.ksu;
 264
 265     tc->setMiscRegNoEffect(TCStatus, tcStatus);
 266 }
 267
 268 } // namespace MipsISA
 269
 270
 271 #endif