src/arch/mips/pagetable.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Jaidev Patwardhan
  29  */
  30
  31 #ifndef __ARCH_MIPS_PAGETABLE_H__
  32 #define __ARCH_MIPS_PAGETABLE_H__
  33
  34 #include "arch/mips/isa_traits.hh"
  35 #include "arch/mips/utility.hh"
  36 #include "arch/mips/vtophys.hh"
  37 #include "config/full_system.hh"
  38
  39 namespace MipsISA {
  40
  41     struct VAddr
  42     {
  43         static const int ImplBits = 43;
  44         static const Addr ImplMask = (ULL(1) << ImplBits) - 1;
  45         static const Addr UnImplMask = ~ImplMask;
  46
  47         VAddr(Addr a) : addr(a) {}
  48         Addr addr;
  49         operator Addr() const { return addr; }
  50         const VAddr &operator=(Addr a) { addr = a; return *this; }
  51
  52         Addr vpn() const { return (addr & ImplMask) >> PageShift; }
  53         Addr page() const { return addr & Page_Mask; }
  54         Addr offset() const { return addr & PageOffset; }
  55
  56         Addr level3() const
  57         { return MipsISA::PteAddr(addr >> PageShift); }
  58         Addr level2() const
  59         { return MipsISA::PteAddr(addr >> NPtePageShift + PageShift); }
  60         Addr level1() const
  61         { return MipsISA::PteAddr(addr >> 2 * NPtePageShift + PageShift); }
  62     };
  63
  64     // ITB/DTB page table entry
  65     struct PTE
  66     {
  67       Addr Mask; // What parts of the VAddr (from bits 28..11) should be used in translation (includes Mask and MaskX from PageMask)
  68       Addr VPN; // Virtual Page Number (/2) (Includes VPN2 + VPN2X .. bits 31..11 from EntryHi)
  69       uint8_t asid; // Address Space ID (8 bits) // Lower 8 bits of EntryHi
  70
  71       bool G;    // Global Bit - Obtained by an *AND* of EntryLo0 and EntryLo1 G bit
  72
  73       /* Contents of Entry Lo0 */
  74       Addr PFN0; // Physical Frame Number - Even
  75       bool D0;   // Even entry Dirty Bit
  76       bool V0;   // Even entry Valid Bit
  77       uint8_t C0; // Cache Coherency Bits - Even
  78
  79       /* Contents of Entry Lo1 */
  80       Addr PFN1; // Physical Frame Number - Odd
  81       bool D1;   // Odd entry Dirty Bit
  82       bool V1;   // Odd entry Valid Bit
  83       uint8_t C1; // Cache Coherency Bits (3 bits)
  84
  85       /* The next few variables are put in as optimizations to reduce TLB lookup overheads */
  86       /* For a given Mask, what is the address shift amount, and what is the OffsetMask */
  87       int AddrShiftAmount;
  88       int OffsetMask;
  89
  90       bool Valid() { return (V0 | V1);};
  91         void serialize(std::ostream &os);
  92         void unserialize(Checkpoint *cp, const std::string &section);
  93     };
  94
  95 };
  96 #endif // __ARCH_MIPS_PAGETABLE_H__
  97