src/arch/mips/pagetable.hh

   1 /*
   2  * Copyright \eN) 2007 MIPS Technologies, Inc.  All Rights Reserved
   3  *
   4  * This software is part of the M5 simulator.
   5  *
   6  * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
   7  * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
   8  * TO THESE TERMS AND CONDITIONS.
   9  *
  10  * Permission is granted to use, copy, create derivative works and
  11  * distribute this software and such derivative works for any purpose,
  12  * so long as (1) the copyright notice above, this grant of permission,
  13  * and the disclaimer below appear in all copies and derivative works
  14  * made, (2) the copyright notice above is augmented as appropriate to
  15  * reflect the addition of any new copyrightable work in a derivative
  16  * work (e.g., Copyright \eN) <Publication Year> Copyright Owner), and (3)
  17  * the name of MIPS Technologies, Inc. (\e$(B!H\e(BMIPS\e$(B!I\e(B) is not used in any
  18  * advertising or publicity pertaining to the use or distribution of
  19  * this software without specific, written prior authorization.
  20  *
  21  * THIS SOFTWARE IS PROVIDED \e$(B!H\e(BAS IS.\e$(B!I\e(B  MIPS MAKES NO WARRANTIES AND
  22  * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
  23  * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  24  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
  25  * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
  26  * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
  27  * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
  28  * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
  29  * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
  30  * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
  31  * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
  32  * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
  33  *
  34  * Authors: Jaidev Patwardhan
  35  *
  36  */
  37
  38 #ifndef __ARCH_MIPS_PAGETABLE_H__
  39 #define __ARCH_MIPS_PAGETABLE_H__
  40
  41 #include "arch/mips/isa_traits.hh"
  42 #include "arch/mips/utility.hh"
  43 #include "config/full_system.hh"
  44
  45 namespace MipsISA {
  46
  47     struct VAddr
  48     {
  49         static const int ImplBits = 43;
  50         static const Addr ImplMask = (ULL(1) << ImplBits) - 1;
  51         static const Addr UnImplMask = ~ImplMask;
  52
  53         VAddr(Addr a) : addr(a) {}
  54         Addr addr;
  55         operator Addr() const { return addr; }
  56         const VAddr &operator=(Addr a) { addr = a; return *this; }
  57
  58         Addr vpn() const { return (addr & ImplMask) >> PageShift; }
  59         Addr page() const { return addr & Page_Mask; }
  60         Addr offset() const { return addr & PageOffset; }
  61
  62         Addr level3() const
  63         { return MipsISA::PteAddr(addr >> PageShift); }
  64         Addr level2() const
  65         { return MipsISA::PteAddr(addr >> NPtePageShift + PageShift); }
  66         Addr level1() const
  67         { return MipsISA::PteAddr(addr >> 2 * NPtePageShift + PageShift); }
  68     };
  69
  70     // ITB/DTB page table entry
  71     struct PTE
  72     {
  73       Addr Mask; // What parts of the VAddr (from bits 28..11) should be used in translation (includes Mask and MaskX from PageMask)
  74       Addr VPN; // Virtual Page Number (/2) (Includes VPN2 + VPN2X .. bits 31..11 from EntryHi)
  75       uint8_t asid; // Address Space ID (8 bits) // Lower 8 bits of EntryHi
  76
  77       bool G;    // Global Bit - Obtained by an *AND* of EntryLo0 and EntryLo1 G bit
  78
  79       /* Contents of Entry Lo0 */
  80       Addr PFN0; // Physical Frame Number - Even
  81       bool D0;   // Even entry Dirty Bit
  82       bool V0;   // Even entry Valid Bit
  83       uint8_t C0; // Cache Coherency Bits - Even
  84
  85       /* Contents of Entry Lo1 */
  86       Addr PFN1; // Physical Frame Number - Odd
  87       bool D1;   // Odd entry Dirty Bit
  88       bool V1;   // Odd entry Valid Bit
  89       uint8_t C1; // Cache Coherency Bits (3 bits)
  90
  91       /* The next few variables are put in as optimizations to reduce TLB lookup overheads */
  92       /* For a given Mask, what is the address shift amount, and what is the OffsetMask */
  93       int AddrShiftAmount;
  94       int OffsetMask;
  95
  96       bool Valid() { return (V0 | V1);};
  97         void serialize(std::ostream &os);
  98         void unserialize(Checkpoint *cp, const std::string &section);
  99     };
 100
 101 };
 102 #endif // __ARCH_MIPS_PAGETABLE_H__
 103