src/arch/mips/pra_constants.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Jaidev Patwardhan
  29  */
  30
  31 #ifndef __ARCH_MIPS_PRA_CONSTANTS_HH__
  32 #define __ARCH_MIPS_PRA_CONSTANTS_HH__
  33
  34 #include "arch/mips/types.hh"
  35 #include "base/bitunion.hh"
  36
  37 namespace MipsISA
  38 {
  39
  40 BitUnion32(IndexReg)
  41     Bitfield<31> p;
  42     // Need to figure out how to put in the TLB specific bits here
  43     // For now, we assume that the entire length is used by the index
  44     // field In reality, Index_HI = N-1, where
  45     // N = Ceiling(log2(TLB Entries))
  46     Bitfield<30, 0> index;
  47 EndBitUnion(IndexReg)
  48
  49 BitUnion32(RandomReg)
  50     // This has a problem similar to the IndexReg index field. We'll keep
  51     // both consistent at 30 for now
  52     Bitfield<30, 0> random;
  53 EndBitUnion(RandomReg)
  54
  55 BitUnion64(EntryLoReg)
  56     Bitfield<63, 30> fill;
  57     Bitfield<29, 6>  pfn;   // Page frame number
  58     Bitfield<5,  3>  c;     // Coherency attribute
  59     Bitfield<2>      d;     // Dirty Bit
  60     Bitfield<1>      v;     // Valid Bit
  61     Bitfield<0>      g;     // Global Bit
  62 EndBitUnion(EntryLoReg)
  63
  64 BitUnion64(ContextReg)
  65     Bitfield<63, 23> pteBase;
  66     Bitfield<22, 4>  badVPN2;
  67     // Bits 3-0 are 0
  68 EndBitUnion(ContextReg)
  69
  70 BitUnion32(PageMaskReg)
  71     // Bits 31-29 are 0
  72     Bitfield<28, 13> mask;
  73     Bitfield<12, 11> maskx;
  74     // Bits 10-0 are zero
  75 EndBitUnion(PageMaskReg)
  76
  77 BitUnion32(PageGrainReg)
  78     Bitfield<31, 30> aseUp;
  79     Bitfield<29>     elpa;
  80     Bitfield<28>     esp;
  81     // Bits 27-13 are zeros
  82     Bitfield<12, 8>  aseDn;
  83     // Bits 7-0 are zeros
  84 EndBitUnion(PageGrainReg)
  85
  86 BitUnion32(WiredReg)
  87     // See note on Index register above
  88     Bitfield<30, 0> wired;
  89 EndBitUnion(WiredReg)
  90
  91 BitUnion32(HWREnaReg)
  92     Bitfield<31, 30> impl;
  93     Bitfield<3,  0>  mask;
  94 EndBitUnion(HWREnaReg)
  95
  96 BitUnion64(EntryHiReg)
  97     Bitfield<63, 62> r;
  98     Bitfield<61, 40> fill;
  99     Bitfield<39, 13> vpn2;
 100     Bitfield<12, 11> vpn2x;
 101     Bitfield<7,  0>  asid;
 102 EndBitUnion(EntryHiReg)
 103
 104 BitUnion32(StatusReg)
 105     SubBitUnion(cu, 31, 28)
 106         Bitfield<31> cu3;
 107         Bitfield<30> cu2;
 108         Bitfield<29> cu1;
 109         Bitfield<28> cu0;
 110     EndSubBitUnion(cu)
 111     Bitfield<27>     rp;
 112     Bitfield<26>     fr;
 113     Bitfield<25>     re;
 114     Bitfield<24>     mx;
 115     Bitfield<23>     px;
 116     Bitfield<22>     bev;
 117     Bitfield<21>     ts;
 118     Bitfield<20>     sr;
 119     Bitfield<19>     nmi;
 120     // Bit 18 is zero
 121     Bitfield<17, 16> impl;
 122     Bitfield<15, 10> ipl;
 123     Bitfield<15>     im7;
 124     Bitfield<14>     im6;
 125     Bitfield<13>     im5;
 126     Bitfield<12>     im4;
 127     Bitfield<11>     im3;
 128     Bitfield<10>     im2;
 129     Bitfield<9>      im1;
 130     Bitfield<8>      im0;
 131     Bitfield<7>      kx;
 132     Bitfield<6>      sx;
 133     Bitfield<5>      ux;
 134     Bitfield<4,  3>  ksu;
 135     Bitfield<4>      um;
 136     Bitfield<3>      r0;
 137     Bitfield<2>      erl;
 138     Bitfield<1>      exl;
 139     Bitfield<0>      ie;
 140 EndBitUnion(StatusReg)
 141
 142 BitUnion32(IntCtlReg)
 143     Bitfield<31, 29> ipti;
 144     Bitfield<28, 26> ippci;
 145     // Bits 26-10 are zeros
 146     Bitfield<9,  5>  vs;
 147     // Bits 4-0 are zeros
 148 EndBitUnion(IntCtlReg)
 149
 150 BitUnion32(SRSCtlReg)
 151     // Bits 31-30 are zeros
 152     Bitfield<29, 26> hss;
 153     // Bits 25-22 are zeros
 154     Bitfield<21, 18> eicss;
 155     // Bits 17-16 are zeros
 156     Bitfield<15, 12> ess;
 157     // Bits 11-10 are zeros
 158     Bitfield<9,  6>  pss;
 159     // Bits 5-4 are zeros
 160     Bitfield<3,  0>  css;
 161 EndBitUnion(SRSCtlReg)
 162
 163 BitUnion32(SRSMapReg)
 164     Bitfield<31, 28> ssv7;
 165     Bitfield<27, 24> ssv6;
 166     Bitfield<23, 20> ssv5;
 167     Bitfield<19, 16> ssv4;
 168     Bitfield<15, 12> ssv3;
 169     Bitfield<11, 8>  ssv2;
 170     Bitfield<7,  4>  ssv1;
 171     Bitfield<3,  0>  ssv0;
 172 EndBitUnion(SRSMapReg)
 173
 174 BitUnion32(CauseReg)
 175     Bitfield<31>     bd;
 176     Bitfield<30>     ti;
 177     Bitfield<29, 28> ce;
 178     Bitfield<27>     dc;
 179     Bitfield<26>     pci;
 180     // Bits 25-24 are zeros
 181     Bitfield<23>     iv;
 182     Bitfield<22>     wp;
 183     // Bits 21-16 are zeros
 184     Bitfield<15, 10> ripl;
 185     Bitfield<15>     ip7;
 186     Bitfield<14>     ip6;
 187     Bitfield<13>     ip5;
 188     Bitfield<12>     ip4;
 189     Bitfield<11>     ip3;
 190     Bitfield<10>     ip2;
 191     Bitfield<9>      ip1;
 192     Bitfield<8>      ip0;
 193     // Bit 7 is zero
 194     Bitfield<6,  2>  excCode;
 195     // Bits 1-0 are zeros
 196 EndBitUnion(CauseReg)
 197
 198 BitUnion32(PRIdReg)
 199     Bitfield<31, 24> coOp;
 200     Bitfield<23, 16> coId;
 201     Bitfield<15, 8>  procId;
 202     Bitfield<7,  0>  rev;
 203 EndBitUnion(PRIdReg)
 204
 205 BitUnion32(EBaseReg)
 206     // Bit 31 is one
 207     // Bit 30 is zero
 208     Bitfield<29, 12> exceptionBase;
 209     // Bits 11-10 are zeros
 210     Bitfield<9,  9>  cpuNum;
 211 EndBitUnion(EBaseReg)
 212
 213 BitUnion32(ConfigReg)
 214     Bitfield<31>     m;
 215     Bitfield<30, 28> k23;
 216     Bitfield<27, 25> ku;
 217     Bitfield<24, 16> impl;
 218     Bitfield<15>     be;
 219     Bitfield<14, 13> at;
 220     Bitfield<12, 10> ar;
 221     Bitfield<9,  7>  mt;
 222     // Bits 6-4 are zeros
 223     Bitfield<3>      vi;
 224     Bitfield<2,  0>  k0;
 225 EndBitUnion(ConfigReg)
 226
 227 BitUnion32(Config1Reg)
 228     Bitfield<31>     m;
 229     Bitfield<30, 25> mmuSize;
 230     Bitfield<24, 22> is;
 231     Bitfield<21, 19> il;
 232     Bitfield<18, 16> ia;
 233     Bitfield<15, 13> ds;
 234     Bitfield<12, 10> dl;
 235     Bitfield<9,  7>  da;
 236     Bitfield<6>      c2;
 237     Bitfield<5>      md;
 238     Bitfield<4>      pc;
 239     Bitfield<3>      wr;
 240     Bitfield<2>      ca;
 241     Bitfield<1>      ep;
 242     Bitfield<0>      fp;
 243 EndBitUnion(Config1Reg)
 244
 245 BitUnion32(Config2Reg)
 246     Bitfield<31>     m;
 247     Bitfield<30, 28> tu;
 248     Bitfield<27, 24> ts;
 249     Bitfield<23, 20> tl;
 250     Bitfield<19, 16> ta;
 251     Bitfield<15, 12> su;
 252     Bitfield<11, 8>  ss;
 253     Bitfield<7,  4>  sl;
 254     Bitfield<3,  0>  sa;
 255 EndBitUnion(Config2Reg)
 256
 257 BitUnion32(Config3Reg)
 258     Bitfield<31> m;
 259     // Bits 30-11 are zeros
 260     Bitfield<10> dspp;
 261     // Bits 9-8 are zeros
 262     Bitfield<7>  lpa;
 263     Bitfield<6>  veic;
 264     Bitfield<5>  vint;
 265     Bitfield<4>  sp;
 266     // Bit 3 is zero
 267     Bitfield<2>  mt;
 268     Bitfield<1>  sm;
 269     Bitfield<0>  tl;
 270 EndBitUnion(Config3Reg)
 271
 272 BitUnion64(WatchLoReg)
 273     Bitfield<63, 3> vaddr;
 274     Bitfield<2>     i;
 275     Bitfield<1>     r;
 276     Bitfield<0>     w;
 277 EndBitUnion(WatchLoReg)
 278
 279 BitUnion32(WatchHiReg)
 280     Bitfield<31>     m;
 281     Bitfield<30>     g;
 282     // Bits 29-24 are zeros
 283     Bitfield<23, 16> asid;
 284     // Bits 15-12 are zeros
 285     Bitfield<11, 3>  mask;
 286     Bitfield<2>      i;
 287     Bitfield<1>      r;
 288     Bitfield<0>      w;
 289 EndBitUnion(WatchHiReg)
 290
 291 BitUnion32(PerfCntCtlReg)
 292     Bitfield<31>    m;
 293     Bitfield<30>    w;
 294     // Bits 29-11 are zeros
 295     Bitfield<10, 5> event;
 296     Bitfield<4>     ie;
 297     Bitfield<3>     u;
 298     Bitfield<2>     s;
 299     Bitfield<1>     k;
 300     Bitfield<0>     exl;
 301 EndBitUnion(PerfCntCtlReg)
 302
 303 BitUnion32(CacheErrReg)
 304     Bitfield<31>     er;
 305     Bitfield<30>     ec;
 306     Bitfield<29>     ed;
 307     Bitfield<28>     et;
 308     Bitfield<27>     es;
 309     Bitfield<26>     ee;
 310     Bitfield<25>     eb;
 311     Bitfield<24, 22> impl;
 312     Bitfield<22, 0>  index;
 313 EndBitUnion(CacheErrReg)
 314
 315 BitUnion32(TagLoReg)
 316     Bitfield<31, 8> pTagLo;
 317     Bitfield<7,  6> pState;
 318     Bitfield<5>     l;
 319     Bitfield<4,  3> impl;
 320     // Bits 2-1 are zeros
 321     Bitfield<0>     p;
 322 EndBitUnion(TagLoReg)
 323
 324 } // namespace MipsISA
 325
 326 #endif