src/arch/mips/regfile/float_regfile.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __ARCH_MIPS_REGFILE_FLOAT_REGFILE_HH__
  30 #define __ARCH_MIPS_REGFILE_FLOAT_REGFILE_HH__
  31
  32 #include "arch/mips/types.hh"
  33 #include "arch/mips/isa_traits.hh"
  34 #include "base/misc.hh"
  35 #include "base/bitfield.hh"
  36 #include "sim/faults.hh"
  37
  38 #include <string>
  39
  40 class Checkpoint;
  41
  42 namespace MipsISA
  43 {
  44     static inline std::string getFloatRegName(RegIndex)
  45     {
  46         return "";
  47     }
  48
  49     const uint32_t MIPS32_QNAN = 0x7fbfffff;
  50     const uint64_t MIPS64_QNAN = ULL(0x7fbfffffffffffff);
  51
  52     enum FPControlRegNums {
  53        FIR = NumFloatArchRegs,
  54        FCCR,
  55        FEXR,
  56        FENR,
  57        FCSR
  58     };
  59
  60     enum FCSRBits {
  61         Inexact = 1,
  62         Underflow,
  63         Overflow,
  64         DivideByZero,
  65         Invalid,
  66         Unimplemented
  67     };
  68
  69     enum FCSRFields {
  70         Flag_Field = 1,
  71         Enable_Field = 6,
  72         Cause_Field = 11
  73     };
  74
  75     const int SingleWidth = 32;
  76     const int SingleBytes = SingleWidth / 4;
  77
  78     const int DoubleWidth = 64;
  79     const int DoubleBytes = DoubleWidth / 4;
  80
  81     const int QuadWidth = 128;
  82     const int QuadBytes = QuadWidth / 4;
  83
  84     class FloatRegFile
  85     {
  86       protected:
  87         FloatReg32 regs[NumFloatRegs];
  88
  89       public:
  90
  91         void clear() { bzero(&regs, sizeof(regs)); }
  92
  93         double readReg(int floatReg, int width, unsigned tid = 0)
  94         {
  95             switch(width)
  96             {
  97               case SingleWidth:
  98                 {
  99                     void *float_ptr = &regs[floatReg];
 100                     return *(float *) float_ptr;
 101                 }
 102
 103               case DoubleWidth:
 104                 {
 105                     uint64_t double_val = (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg];
 106                     void *double_ptr = &double_val;
 107                     return *(double *) double_ptr;
 108                 }
 109
 110               default:
 111                 panic("Attempted to read a %d bit floating point register!", width);
 112             }
 113         }
 114
 115         FloatRegBits readRegBits(int floatReg, int width, unsigned tid = 0)
 116         {
 117             if (floatReg < NumFloatArchRegs - 1) {
 118                 switch(width)
 119                 {
 120                   case SingleWidth:
 121                     return regs[floatReg];
 122
 123                   case DoubleWidth:
 124                     return (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg];
 125
 126                   default:
 127                     panic("Attempted to read a %d bit floating point register!", width);
 128                 }
 129             } else {
 130                 if (width > SingleWidth)
 131                     assert("Control Regs are only 32 bits wide");
 132
 133                 return regs[floatReg];
 134             }
 135         }
 136
 137         Fault setReg(int floatReg, const FloatRegVal &val, int width, unsigned tid = 0)
 138         {
 139             using namespace std;
 140             switch(width)
 141             {
 142               case SingleWidth:
 143                 {
 144                     float temp = val;
 145                     void *float_ptr = &temp;
 146                     regs[floatReg] = *(FloatReg32 *) float_ptr;
 147                     break;
 148                 }
 149
 150               case DoubleWidth:
 151                 {
 152                     const void *double_ptr = &val;
 153                     FloatReg64 temp_double = *(FloatReg64 *) double_ptr;
 154                     regs[floatReg + 1] = bits(temp_double, 63, 32);
 155                     regs[floatReg] = bits(temp_double, 31, 0);
 156                     break;
 157                 }
 158
 159               default:
 160                 panic("Attempted to read a %d bit floating point register!", width);
 161             }
 162
 163             return NoFault;
 164         }
 165
 166         Fault setRegBits(int floatReg, const FloatRegBits &val, int width, unsigned tid = 0)
 167         {
 168             using namespace std;
 169
 170             switch(width)
 171             {
 172               case SingleWidth:
 173                 regs[floatReg] = val;
 174                 break;
 175
 176               case DoubleWidth:
 177                 regs[floatReg + 1] = bits(val, 63, 32);
 178                 regs[floatReg] = bits(val, 31, 0);
 179                 break;
 180
 181               default:
 182                 panic("Attempted to read a %d bit floating point register!", width);
 183             }
 184             return NoFault;
 185         }
 186
 187         void serialize(std::ostream &os);
 188
 189         void unserialize(Checkpoint *cp, const std::string &section);
 190     };
 191
 192 } // namespace MipsISA
 193
 194 #endif