7d100a9054edb4940ade11e5d193d9ea3d508c23
[gem5.git] / src / arch / mips / regfile / regfile.hh
1 /*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 */
30
31 #ifndef __ARCH_MIPS_REGFILE_REGFILE_HH__
32 #define __ARCH_MIPS_REGFILE_REGFILE_HH__
33
34 #include "arch/mips/types.hh"
35 #include "arch/mips/isa_traits.hh"
36 //#include "arch/mips/mt.hh"
37 #include "arch/mips/regfile/int_regfile.hh"
38 #include "arch/mips/regfile/float_regfile.hh"
39 #include "arch/mips/regfile/misc_regfile.hh"
40 //#include "cpu/base.hh"
41 #include "sim/faults.hh"
42
43 class Checkpoint;
44 class BaseCPU;
45
46 namespace MipsISA
47 {
48 class RegFile {
49 protected:
50 Addr pc; // program counter
51 Addr npc; // next-cycle program counter
52 Addr nnpc; // next-next-cycle program counter
53 // used to implement branch delay slot
54 // not real register
55
56 IntRegFile intRegFile; // (signed) integer register file
57 FloatRegFile floatRegFile; // floating point register file
58 MiscRegFile miscRegFile; // control register file
59
60 public:
61 void clear();
62 void reset(std::string core_name, unsigned num_threads, unsigned num_vpes, BaseCPU *_cpu);
63 MiscRegFile *getMiscRegFilePtr();
64
65 IntReg readIntReg(int intReg);
66 Fault setIntReg(int intReg, const IntReg &val);
67
68
69 MiscReg readMiscRegNoEffect(int miscReg, unsigned tid = 0);
70 MiscReg readMiscReg(int miscReg, ThreadContext *tc,
71 unsigned tid = 0);
72 void setMiscRegNoEffect(int miscReg, const MiscReg &val, unsigned tid = 0);
73 void setMiscReg(int miscReg, const MiscReg &val,
74 ThreadContext * tc, unsigned tid = 0);
75
76 FloatRegVal readFloatReg(int floatReg);
77 FloatRegVal readFloatReg(int floatReg, int width);
78 FloatRegBits readFloatRegBits(int floatReg);
79 FloatRegBits readFloatRegBits(int floatReg, int width);
80 Fault setFloatReg(int floatReg, const FloatRegVal &val);
81 Fault setFloatReg(int floatReg, const FloatRegVal &val, int width);
82 Fault setFloatRegBits(int floatReg, const FloatRegBits &val);
83 Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width);
84
85
86 void setShadowSet(int css);
87
88 int instAsid();
89 int dataAsid();
90
91 public:
92 Addr readPC();
93 void setPC(Addr val);
94
95 Addr readNextPC();
96 void setNextPC(Addr val);
97
98 Addr readNextNPC();
99 void setNextNPC(Addr val);
100
101 void serialize(std::ostream &os);
102 void unserialize(Checkpoint *cp, const std::string &section);
103
104 void changeContext(RegContextParam param, RegContextVal val)
105 {
106 }
107
108 };
109
110 } // namespace MipsISA
111
112 #endif