src/arch/mips/regfile.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * Copyright (c) 2007 MIPS Technologies, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * Authors: Gabe Black
  30  *          Ali Saidi
  31  *          Korey Sewell
  32  */
  33
  34 #ifndef __ARCH_MIPS_REGFILE_REGFILE_HH__
  35 #define __ARCH_MIPS_REGFILE_REGFILE_HH__
  36
  37 #include "arch/mips/types.hh"
  38 #include "arch/mips/isa_traits.hh"
  39 #include "arch/mips/mt.hh"
  40 #include "arch/mips/regfile/int_regfile.hh"
  41 #include "arch/mips/regfile/float_regfile.hh"
  42 #include "arch/mips/regfile/misc_regfile.hh"
  43 #include "sim/faults.hh"
  44
  45 class Checkpoint;
  46 class ThreadContext;
  47
  48 using namespace MipsISA;
  49
  50 void RegFile::clear()
  51 {
  52     intRegFile.clear();
  53     floatRegFile.clear();
  54     miscRegFile.clear();
  55 }
  56
  57 void RegFile::reset(std::string core_name, unsigned num_threads, unsigned num_vpes)
  58 {
  59     bzero(&intRegFile, sizeof(intRegFile));
  60     bzero(&floatRegFile, sizeof(floatRegFile));
  61     miscRegFile.reset(core_name, num_threads, num_vpes);
  62 }
  63
  64 IntReg RegFile::readIntReg(int intReg)
  65 {
  66     return intRegFile.readReg(intReg);
  67 }
  68
  69 Fault RegFile::setIntReg(int intReg, const IntReg &val)
  70 {
  71     return intRegFile.setReg(intReg, val);
  72 }
  73
  74 MiscReg RegFile::readMiscRegNoEffect(int miscReg, unsigned tid = 0)
  75 {
  76     return miscRegFile.readRegNoEffect(miscReg, tid);
  77 }
  78
  79 MiscReg RegFile::readMiscReg(int miscReg, ThreadContext *tc,
  80                              unsigned tid = 0)
  81 {
  82     return miscRegFile.readReg(miscReg, tc, tid);
  83 }
  84
  85 void RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val, unsigned tid = 0)
  86 {
  87     miscRegFile.setRegNoEffect(miscReg, val, tid);
  88 }
  89
  90 void RegFile::setMiscReg(int miscReg, const MiscReg &val,
  91                          ThreadContext * tc, unsigned tid = 0)
  92 {
  93     miscRegFile.setReg(miscReg, val, tc, tid);
  94 }
  95
  96 FloatRegVal RegFile::readFloatReg(int floatReg)
  97 {
  98     return floatRegFile.readReg(floatReg,SingleWidth);
  99 }
 100
 101 FloatRegVal RegFile::readFloatReg(int floatReg, int width)
 102 {
 103     return floatRegFile.readReg(floatReg,width);
 104 }
 105
 106 FloatRegBits RegFile::readFloatRegBits(int floatReg)
 107 {
 108     return floatRegFile.readRegBits(floatReg,SingleWidth);
 109 }
 110
 111 FloatRegBits RegFile::readFloatRegBits(int floatReg, int width)
 112 {
 113     return floatRegFile.readRegBits(floatReg,width);
 114 }
 115
 116 Fault RegFile::setFloatReg(int floatReg, const FloatRegVal &val)
 117 {
 118     return floatRegFile.setReg(floatReg, val, SingleWidth);
 119 }
 120
 121 Fault RegFile::setFloatReg(int floatReg, const FloatRegVal &val, int width)
 122 {
 123     return floatRegFile.setReg(floatReg, val, width);
 124 }
 125
 126 Fault RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val)
 127 {
 128     return floatRegFile.setRegBits(floatReg, val, SingleWidth);
 129 }
 130
 131 Fault RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
 132 {
 133     return floatRegFile.setRegBits(floatReg, val, width);
 134 }
 135
 136 Addr RegFile::readPC()
 137 {
 138     return pc;
 139 }
 140
 141 void RegFile::setPC(Addr val)
 142 {
 143     pc = val;
 144 }
 145
 146 Addr RegFile::readNextPC()
 147 {
 148     return npc;
 149 }
 150
 151 void RegFile::setNextPC(Addr val)
 152 {
 153     npc = val;
 154 }
 155
 156 Addr RegFile::readNextNPC()
 157 {
 158     return nnpc;
 159 }
 160
 161 void RegFile::setNextNPC(Addr val)
 162 {
 163     nnpc = val;
 164 }
 165
 166 void
 167 RegFile::serialize(std::ostream &os)
 168 {
 169     intRegFile.serialize(os);
 170     floatRegFile.serialize(os);
 171     miscRegFile.serialize(os);
 172
 173     SERIALIZE_SCALAR(pc);
 174     SERIALIZE_SCALAR(npc);
 175     SERIALIZE_SCALAR(nnpc);
 176 }
 177
 178
 179 void
 180 RegFile::unserialize(Checkpoint *cp, const std::string &section)
 181 {
 182     intRegFile.unserialize(cp, section);
 183     floatRegFile.unserialize(cp, section);
 184     miscRegFile.unserialize(cp, section);
 185     UNSERIALIZE_SCALAR(pc);
 186     UNSERIALIZE_SCALAR(npc);
 187     UNSERIALIZE_SCALAR(nnpc);
 188
 189 }
 190
 191 static inline int flattenIntIndex(ThreadContext * tc, int reg)
 192 {
 193     return reg;
 194 }
 195
 196 void
 197 MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest)
 198 {
 199     panic("Copy Regs Not Implemented Yet\n");
 200 }
 201
 202 void
 203 MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest);
 204 {
 205     panic("Copy Regs Not Implemented Yet\n");
 206 }
 207
 208 void
 209 MipsISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
 210 {
 211     panic("Copy Misc. Regs Not Implemented Yet\n");
 212 }