src/arch/mips/registers.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * Copyright (c) 2007 MIPS Technologies, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 #ifndef __ARCH_MIPS_REGISTERS_HH__
  31 #define __ARCH_MIPS_REGISTERS_HH__
  32
  33 #include "arch/generic/vec_pred_reg.hh"
  34 #include "arch/generic/vec_reg.hh"
  35 #include "arch/mips/generated/max_inst_regs.hh"
  36 #include "base/logging.hh"
  37 #include "base/types.hh"
  38
  39 class ThreadContext;
  40
  41 namespace MipsISA
  42 {
  43
  44 using MipsISAInst::MaxInstSrcRegs;
  45 using MipsISAInst::MaxInstDestRegs;
  46 using MipsISAInst::MaxMiscDestRegs;
  47
  48 // Constants Related to the number of registers
  49 const int NumIntArchRegs = 32;
  50 const int NumIntSpecialRegs = 9;
  51 const int NumFloatArchRegs = 32;
  52 const int NumFloatSpecialRegs = 5;
  53
  54 const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
  55 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;        //HI & LO Regs
  56 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
  57 const int NumVecRegs = 1;  // Not applicable to MIPS
  58                            // (1 to prevent warnings)
  59 const int NumVecPredRegs = 1;  // Not applicable to MIPS
  60                                // (1 to prevent warnings)
  61 const int NumCCRegs = 0;
  62
  63 const uint32_t MIPS32_QNAN = 0x7fbfffff;
  64 const uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff);
  65
  66 enum FPControlRegNums {
  67    FLOATREG_FIR = NumFloatArchRegs,
  68    FLOATREG_FCCR,
  69    FLOATREG_FEXR,
  70    FLOATREG_FENR,
  71    FLOATREG_FCSR
  72 };
  73
  74 enum FCSRBits {
  75     Inexact = 1,
  76     Underflow,
  77     Overflow,
  78     DivideByZero,
  79     Invalid,
  80     Unimplemented
  81 };
  82
  83 enum FCSRFields {
  84     Flag_Field = 1,
  85     Enable_Field = 6,
  86     Cause_Field = 11
  87 };
  88
  89 enum MiscIntRegNums {
  90    INTREG_LO = NumIntArchRegs,
  91    INTREG_DSP_LO0 = INTREG_LO,
  92    INTREG_HI,
  93    INTREG_DSP_HI0 = INTREG_HI,
  94    INTREG_DSP_ACX0,
  95    INTREG_DSP_LO1,
  96    INTREG_DSP_HI1,
  97    INTREG_DSP_ACX1,
  98    INTREG_DSP_LO2,
  99    INTREG_DSP_HI2,
 100    INTREG_DSP_ACX2,
 101    INTREG_DSP_LO3,
 102    INTREG_DSP_HI3,
 103    INTREG_DSP_ACX3,
 104    INTREG_DSP_CONTROL
 105 };
 106
 107 // semantically meaningful register indices
 108 const int ZeroReg = 0;
 109 const int SyscallSuccessReg = 7;
 110 const int FirstArgumentReg = 4;
 111 const int ReturnValueReg = 2;
 112
 113 const int StackPointerReg = 29;
 114
 115 const int SyscallPseudoReturnReg = 3;
 116
 117 // Enumerate names for 'Control' Registers in the CPU
 118 // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
 119 // (Register Number-Register Select) Summary of Register
 120 //------------------------------------------------------
 121 // The first set of names classify the CP0 names as Register Banks
 122 // for easy indexing when using the 'RD + SEL' index combination
 123 // in CP0 instructions.
 124 enum MiscRegIndex{
 125     MISCREG_INDEX = 0,       //Bank 0: 0 - 3
 126     MISCREG_MVP_CONTROL,
 127     MISCREG_MVP_CONF0,
 128     MISCREG_MVP_CONF1,
 129
 130     MISCREG_CP0_RANDOM = 8,      //Bank 1: 8 - 15
 131     MISCREG_VPE_CONTROL,
 132     MISCREG_VPE_CONF0,
 133     MISCREG_VPE_CONF1,
 134     MISCREG_YQMASK,
 135     MISCREG_VPE_SCHEDULE,
 136     MISCREG_VPE_SCHEFBACK,
 137     MISCREG_VPE_OPT,
 138
 139     MISCREG_ENTRYLO0 = 16,   //Bank 2: 16 - 23
 140     MISCREG_TC_STATUS,
 141     MISCREG_TC_BIND,
 142     MISCREG_TC_RESTART,
 143     MISCREG_TC_HALT,
 144     MISCREG_TC_CONTEXT,
 145     MISCREG_TC_SCHEDULE,
 146     MISCREG_TC_SCHEFBACK,
 147
 148     MISCREG_ENTRYLO1 = 24,   // Bank 3: 24
 149
 150     MISCREG_CONTEXT = 32,    // Bank 4: 32 - 33
 151     MISCREG_CONTEXT_CONFIG,
 152
 153     MISCREG_PAGEMASK = 40, //Bank 5: 40 - 41
 154     MISCREG_PAGEGRAIN = 41,
 155
 156     MISCREG_WIRED = 48,          //Bank 6:48-55
 157     MISCREG_SRS_CONF0,
 158     MISCREG_SRS_CONF1,
 159     MISCREG_SRS_CONF2,
 160     MISCREG_SRS_CONF3,
 161     MISCREG_SRS_CONF4,
 162
 163     MISCREG_HWRENA = 56,         //Bank 7: 56-63
 164
 165     MISCREG_BADVADDR = 64,       //Bank 8: 64-71
 166
 167     MISCREG_COUNT = 72,          //Bank 9: 72-79
 168
 169     MISCREG_ENTRYHI = 80,        //Bank 10: 80-87
 170
 171     MISCREG_COMPARE = 88,        //Bank 11: 88-95
 172
 173     MISCREG_STATUS = 96,         //Bank 12: 96-103
 174     MISCREG_INTCTL,
 175     MISCREG_SRSCTL,
 176     MISCREG_SRSMAP,
 177
 178     MISCREG_CAUSE = 104,         //Bank 13: 104-111
 179
 180     MISCREG_EPC = 112,           //Bank 14: 112-119
 181
 182     MISCREG_PRID = 120,          //Bank 15: 120-127,
 183     MISCREG_EBASE,
 184
 185     MISCREG_CONFIG = 128,        //Bank 16: 128-135
 186     MISCREG_CONFIG1,
 187     MISCREG_CONFIG2,
 188     MISCREG_CONFIG3,
 189     MISCREG_CONFIG4,
 190     MISCREG_CONFIG5,
 191     MISCREG_CONFIG6,
 192     MISCREG_CONFIG7,
 193
 194
 195     MISCREG_LLADDR = 136,        //Bank 17: 136-143
 196
 197     MISCREG_WATCHLO0 = 144,      //Bank 18: 144-151
 198     MISCREG_WATCHLO1,
 199     MISCREG_WATCHLO2,
 200     MISCREG_WATCHLO3,
 201     MISCREG_WATCHLO4,
 202     MISCREG_WATCHLO5,
 203     MISCREG_WATCHLO6,
 204     MISCREG_WATCHLO7,
 205
 206     MISCREG_WATCHHI0 = 152,     //Bank 19: 152-159
 207     MISCREG_WATCHHI1,
 208     MISCREG_WATCHHI2,
 209     MISCREG_WATCHHI3,
 210     MISCREG_WATCHHI4,
 211     MISCREG_WATCHHI5,
 212     MISCREG_WATCHHI6,
 213     MISCREG_WATCHHI7,
 214
 215     MISCREG_XCCONTEXT64 = 160, //Bank 20: 160-167
 216
 217                        //Bank 21: 168-175
 218
 219                        //Bank 22: 176-183
 220
 221     MISCREG_DEBUG = 184,       //Bank 23: 184-191
 222     MISCREG_TRACE_CONTROL1,
 223     MISCREG_TRACE_CONTROL2,
 224     MISCREG_USER_TRACE_DATA,
 225     MISCREG_TRACE_BPC,
 226
 227     MISCREG_DEPC = 192,        //Bank 24: 192-199
 228
 229     MISCREG_PERFCNT0 = 200,    //Bank 25: 200-207
 230     MISCREG_PERFCNT1,
 231     MISCREG_PERFCNT2,
 232     MISCREG_PERFCNT3,
 233     MISCREG_PERFCNT4,
 234     MISCREG_PERFCNT5,
 235     MISCREG_PERFCNT6,
 236     MISCREG_PERFCNT7,
 237
 238     MISCREG_ERRCTL = 208,      //Bank 26: 208-215
 239
 240     MISCREG_CACHEERR0 = 216,   //Bank 27: 216-223
 241     MISCREG_CACHEERR1,
 242     MISCREG_CACHEERR2,
 243     MISCREG_CACHEERR3,
 244
 245     MISCREG_TAGLO0 = 224,      //Bank 28: 224-231
 246     MISCREG_DATALO1,
 247     MISCREG_TAGLO2,
 248     MISCREG_DATALO3,
 249     MISCREG_TAGLO4,
 250     MISCREG_DATALO5,
 251     MISCREG_TAGLO6,
 252     MISCREG_DATALO7,
 253
 254     MISCREG_TAGHI0 = 232,      //Bank 29: 232-239
 255     MISCREG_DATAHI1,
 256     MISCREG_TAGHI2,
 257     MISCREG_DATAHI3,
 258     MISCREG_TAGHI4,
 259     MISCREG_DATAHI5,
 260     MISCREG_TAGHI6,
 261     MISCREG_DATAHI7,
 262
 263
 264     MISCREG_ERROR_EPC = 240,    //Bank 30: 240-247
 265
 266     MISCREG_DESAVE = 248,       //Bank 31: 248-256
 267
 268     MISCREG_LLFLAG = 257,
 269     MISCREG_TP_VALUE,
 270
 271     MISCREG_NUMREGS
 272 };
 273
 274 const int NumMiscRegs = MISCREG_NUMREGS;
 275
 276 // Not applicable to MIPS
 277 using VecElem = ::DummyVecElem;
 278 using VecReg = ::DummyVecReg;
 279 using ConstVecReg = ::DummyConstVecReg;
 280 using VecRegContainer = ::DummyVecRegContainer;
 281 constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
 282 constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;
 283
 284 // Not applicable to MIPS
 285 using VecPredReg = ::DummyVecPredReg;
 286 using ConstVecPredReg = ::DummyConstVecPredReg;
 287 using VecPredRegContainer = ::DummyVecPredRegContainer;
 288 constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
 289 constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
 290
 291 } // namespace MipsISA
 292
 293 #endif