2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
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15 * this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * Authors: Korey Sewell
32 #ifndef __ARCH_MIPS_REGISTERS_HH__
33 #define __ARCH_MIPS_REGISTERS_HH__
35 #include "arch/mips/generated/max_inst_regs.hh"
36 #include "base/misc.hh"
37 #include "base/types.hh"
44 using MipsISAInst::MaxInstSrcRegs;
45 using MipsISAInst::MaxInstDestRegs;
46 using MipsISAInst::MaxMiscDestRegs;
48 // Constants Related to the number of registers
49 const int NumIntArchRegs = 32;
50 const int NumIntSpecialRegs = 9;
51 const int NumFloatArchRegs = 32;
52 const int NumFloatSpecialRegs = 5;
54 const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
55 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs
56 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
57 const int NumCCRegs = 0;
59 const uint32_t MIPS32_QNAN = 0x7fbfffff;
60 const uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff);
62 enum FPControlRegNums {
63 FLOATREG_FIR = NumFloatArchRegs,
86 INTREG_LO = NumIntArchRegs,
87 INTREG_DSP_LO0 = INTREG_LO,
89 INTREG_DSP_HI0 = INTREG_HI,
103 // semantically meaningful register indices
104 const int ZeroReg = 0;
105 const int AssemblerReg = 1;
106 const int SyscallSuccessReg = 7;
107 const int FirstArgumentReg = 4;
108 const int ReturnValueReg = 2;
110 const int KernelReg0 = 26;
111 const int KernelReg1 = 27;
112 const int GlobalPointerReg = 28;
113 const int StackPointerReg = 29;
114 const int FramePointerReg = 30;
115 const int ReturnAddressReg = 31;
117 const int SyscallPseudoReturnReg = 3;
119 // Enumerate names for 'Control' Registers in the CPU
120 // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
121 // (Register Number-Register Select) Summary of Register
122 //------------------------------------------------------
123 // The first set of names classify the CP0 names as Register Banks
124 // for easy indexing when using the 'RD + SEL' index combination
125 // in CP0 instructions.
127 MISCREG_INDEX = 0, //Bank 0: 0 - 3
132 MISCREG_CP0_RANDOM = 8, //Bank 1: 8 - 15
137 MISCREG_VPE_SCHEDULE,
138 MISCREG_VPE_SCHEFBACK,
141 MISCREG_ENTRYLO0 = 16, //Bank 2: 16 - 23
148 MISCREG_TC_SCHEFBACK,
150 MISCREG_ENTRYLO1 = 24, // Bank 3: 24
152 MISCREG_CONTEXT = 32, // Bank 4: 32 - 33
153 MISCREG_CONTEXT_CONFIG,
155 MISCREG_PAGEMASK = 40, //Bank 5: 40 - 41
156 MISCREG_PAGEGRAIN = 41,
158 MISCREG_WIRED = 48, //Bank 6:48-55
165 MISCREG_HWRENA = 56, //Bank 7: 56-63
167 MISCREG_BADVADDR = 64, //Bank 8: 64-71
169 MISCREG_COUNT = 72, //Bank 9: 72-79
171 MISCREG_ENTRYHI = 80, //Bank 10: 80-87
173 MISCREG_COMPARE = 88, //Bank 11: 88-95
175 MISCREG_STATUS = 96, //Bank 12: 96-103
180 MISCREG_CAUSE = 104, //Bank 13: 104-111
182 MISCREG_EPC = 112, //Bank 14: 112-119
184 MISCREG_PRID = 120, //Bank 15: 120-127,
187 MISCREG_CONFIG = 128, //Bank 16: 128-135
197 MISCREG_LLADDR = 136, //Bank 17: 136-143
199 MISCREG_WATCHLO0 = 144, //Bank 18: 144-151
208 MISCREG_WATCHHI0 = 152, //Bank 19: 152-159
217 MISCREG_XCCONTEXT64 = 160, //Bank 20: 160-167
223 MISCREG_DEBUG = 184, //Bank 23: 184-191
224 MISCREG_TRACE_CONTROL1,
225 MISCREG_TRACE_CONTROL2,
226 MISCREG_USER_TRACE_DATA,
229 MISCREG_DEPC = 192, //Bank 24: 192-199
231 MISCREG_PERFCNT0 = 200, //Bank 25: 200-207
240 MISCREG_ERRCTL = 208, //Bank 26: 208-215
242 MISCREG_CACHEERR0 = 216, //Bank 27: 216-223
247 MISCREG_TAGLO0 = 224, //Bank 28: 224-231
256 MISCREG_TAGHI0 = 232, //Bank 29: 232-239
266 MISCREG_ERROR_EPC = 240, //Bank 30: 240-247
268 MISCREG_DESAVE = 248, //Bank 31: 248-256
270 MISCREG_LLFLAG = 257,
276 const int NumMiscRegs = MISCREG_NUMREGS;
278 // These help enumerate all the registers for dependence tracking.
279 const int FP_Reg_Base = NumIntRegs;
280 const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
281 const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0
282 const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
284 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
286 typedef uint16_t RegIndex;
288 typedef uint32_t IntReg;
290 // floating point register file entry type
291 typedef uint32_t FloatRegBits;
292 typedef float FloatReg;
294 // cop-0/cop-1 system control register
295 typedef uint64_t MiscReg;
297 // dummy typedef since we don't have CC regs
298 typedef uint8_t CCReg;
306 } // namespace MipsISA