src/arch/mips/registers.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * Copyright (c) 2007 MIPS Technologies, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 #ifndef __ARCH_MIPS_REGISTERS_HH__
  31 #define __ARCH_MIPS_REGISTERS_HH__
  32
  33 #include "arch/generic/vec_pred_reg.hh"
  34 #include "arch/generic/vec_reg.hh"
  35 #include "arch/mips/generated/max_inst_regs.hh"
  36 #include "base/logging.hh"
  37 #include "base/types.hh"
  38
  39 class ThreadContext;
  40
  41 namespace MipsISA
  42 {
  43
  44 using MipsISAInst::MaxInstSrcRegs;
  45 using MipsISAInst::MaxInstDestRegs;
  46 using MipsISAInst::MaxMiscDestRegs;
  47
  48 // Constants Related to the number of registers
  49 const int NumIntArchRegs = 32;
  50 const int NumIntSpecialRegs = 9;
  51 const int NumFloatArchRegs = 32;
  52 const int NumFloatSpecialRegs = 5;
  53
  54 const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
  55 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;        //HI & LO Regs
  56 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
  57 const int NumVecRegs = 1;  // Not applicable to MIPS
  58                            // (1 to prevent warnings)
  59 const int NumVecPredRegs = 1;  // Not applicable to MIPS
  60                                // (1 to prevent warnings)
  61 const int NumCCRegs = 0;
  62
  63 const uint32_t MIPS32_QNAN = 0x7fbfffff;
  64 const uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff);
  65
  66 enum FPControlRegNums {
  67    FLOATREG_FIR = NumFloatArchRegs,
  68    FLOATREG_FCCR,
  69    FLOATREG_FEXR,
  70    FLOATREG_FENR,
  71    FLOATREG_FCSR
  72 };
  73
  74 enum FCSRBits {
  75     Inexact = 1,
  76     Underflow,
  77     Overflow,
  78     DivideByZero,
  79     Invalid,
  80     Unimplemented
  81 };
  82
  83 enum FCSRFields {
  84     Flag_Field = 1,
  85     Enable_Field = 6,
  86     Cause_Field = 11
  87 };
  88
  89 enum MiscIntRegNums {
  90    INTREG_LO = NumIntArchRegs,
  91    INTREG_DSP_LO0 = INTREG_LO,
  92    INTREG_HI,
  93    INTREG_DSP_HI0 = INTREG_HI,
  94    INTREG_DSP_ACX0,
  95    INTREG_DSP_LO1,
  96    INTREG_DSP_HI1,
  97    INTREG_DSP_ACX1,
  98    INTREG_DSP_LO2,
  99    INTREG_DSP_HI2,
 100    INTREG_DSP_ACX2,
 101    INTREG_DSP_LO3,
 102    INTREG_DSP_HI3,
 103    INTREG_DSP_ACX3,
 104    INTREG_DSP_CONTROL
 105 };
 106
 107 // semantically meaningful register indices
 108 const int ZeroReg = 0;
 109 const int AssemblerReg = 1;
 110 const int SyscallSuccessReg = 7;
 111 const int FirstArgumentReg = 4;
 112 const int ReturnValueReg = 2;
 113
 114 const int KernelReg0 = 26;
 115 const int KernelReg1 = 27;
 116 const int GlobalPointerReg = 28;
 117 const int StackPointerReg = 29;
 118 const int FramePointerReg = 30;
 119 const int ReturnAddressReg = 31;
 120
 121 const int SyscallPseudoReturnReg = 3;
 122
 123 // Enumerate names for 'Control' Registers in the CPU
 124 // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
 125 // (Register Number-Register Select) Summary of Register
 126 //------------------------------------------------------
 127 // The first set of names classify the CP0 names as Register Banks
 128 // for easy indexing when using the 'RD + SEL' index combination
 129 // in CP0 instructions.
 130 enum MiscRegIndex{
 131     MISCREG_INDEX = 0,       //Bank 0: 0 - 3
 132     MISCREG_MVP_CONTROL,
 133     MISCREG_MVP_CONF0,
 134     MISCREG_MVP_CONF1,
 135
 136     MISCREG_CP0_RANDOM = 8,      //Bank 1: 8 - 15
 137     MISCREG_VPE_CONTROL,
 138     MISCREG_VPE_CONF0,
 139     MISCREG_VPE_CONF1,
 140     MISCREG_YQMASK,
 141     MISCREG_VPE_SCHEDULE,
 142     MISCREG_VPE_SCHEFBACK,
 143     MISCREG_VPE_OPT,
 144
 145     MISCREG_ENTRYLO0 = 16,   //Bank 2: 16 - 23
 146     MISCREG_TC_STATUS,
 147     MISCREG_TC_BIND,
 148     MISCREG_TC_RESTART,
 149     MISCREG_TC_HALT,
 150     MISCREG_TC_CONTEXT,
 151     MISCREG_TC_SCHEDULE,
 152     MISCREG_TC_SCHEFBACK,
 153
 154     MISCREG_ENTRYLO1 = 24,   // Bank 3: 24
 155
 156     MISCREG_CONTEXT = 32,    // Bank 4: 32 - 33
 157     MISCREG_CONTEXT_CONFIG,
 158
 159     MISCREG_PAGEMASK = 40, //Bank 5: 40 - 41
 160     MISCREG_PAGEGRAIN = 41,
 161
 162     MISCREG_WIRED = 48,          //Bank 6:48-55
 163     MISCREG_SRS_CONF0,
 164     MISCREG_SRS_CONF1,
 165     MISCREG_SRS_CONF2,
 166     MISCREG_SRS_CONF3,
 167     MISCREG_SRS_CONF4,
 168
 169     MISCREG_HWRENA = 56,         //Bank 7: 56-63
 170
 171     MISCREG_BADVADDR = 64,       //Bank 8: 64-71
 172
 173     MISCREG_COUNT = 72,          //Bank 9: 72-79
 174
 175     MISCREG_ENTRYHI = 80,        //Bank 10: 80-87
 176
 177     MISCREG_COMPARE = 88,        //Bank 11: 88-95
 178
 179     MISCREG_STATUS = 96,         //Bank 12: 96-103
 180     MISCREG_INTCTL,
 181     MISCREG_SRSCTL,
 182     MISCREG_SRSMAP,
 183
 184     MISCREG_CAUSE = 104,         //Bank 13: 104-111
 185
 186     MISCREG_EPC = 112,           //Bank 14: 112-119
 187
 188     MISCREG_PRID = 120,          //Bank 15: 120-127,
 189     MISCREG_EBASE,
 190
 191     MISCREG_CONFIG = 128,        //Bank 16: 128-135
 192     MISCREG_CONFIG1,
 193     MISCREG_CONFIG2,
 194     MISCREG_CONFIG3,
 195     MISCREG_CONFIG4,
 196     MISCREG_CONFIG5,
 197     MISCREG_CONFIG6,
 198     MISCREG_CONFIG7,
 199
 200
 201     MISCREG_LLADDR = 136,        //Bank 17: 136-143
 202
 203     MISCREG_WATCHLO0 = 144,      //Bank 18: 144-151
 204     MISCREG_WATCHLO1,
 205     MISCREG_WATCHLO2,
 206     MISCREG_WATCHLO3,
 207     MISCREG_WATCHLO4,
 208     MISCREG_WATCHLO5,
 209     MISCREG_WATCHLO6,
 210     MISCREG_WATCHLO7,
 211
 212     MISCREG_WATCHHI0 = 152,     //Bank 19: 152-159
 213     MISCREG_WATCHHI1,
 214     MISCREG_WATCHHI2,
 215     MISCREG_WATCHHI3,
 216     MISCREG_WATCHHI4,
 217     MISCREG_WATCHHI5,
 218     MISCREG_WATCHHI6,
 219     MISCREG_WATCHHI7,
 220
 221     MISCREG_XCCONTEXT64 = 160, //Bank 20: 160-167
 222
 223                        //Bank 21: 168-175
 224
 225                        //Bank 22: 176-183
 226
 227     MISCREG_DEBUG = 184,       //Bank 23: 184-191
 228     MISCREG_TRACE_CONTROL1,
 229     MISCREG_TRACE_CONTROL2,
 230     MISCREG_USER_TRACE_DATA,
 231     MISCREG_TRACE_BPC,
 232
 233     MISCREG_DEPC = 192,        //Bank 24: 192-199
 234
 235     MISCREG_PERFCNT0 = 200,    //Bank 25: 200-207
 236     MISCREG_PERFCNT1,
 237     MISCREG_PERFCNT2,
 238     MISCREG_PERFCNT3,
 239     MISCREG_PERFCNT4,
 240     MISCREG_PERFCNT5,
 241     MISCREG_PERFCNT6,
 242     MISCREG_PERFCNT7,
 243
 244     MISCREG_ERRCTL = 208,      //Bank 26: 208-215
 245
 246     MISCREG_CACHEERR0 = 216,   //Bank 27: 216-223
 247     MISCREG_CACHEERR1,
 248     MISCREG_CACHEERR2,
 249     MISCREG_CACHEERR3,
 250
 251     MISCREG_TAGLO0 = 224,      //Bank 28: 224-231
 252     MISCREG_DATALO1,
 253     MISCREG_TAGLO2,
 254     MISCREG_DATALO3,
 255     MISCREG_TAGLO4,
 256     MISCREG_DATALO5,
 257     MISCREG_TAGLO6,
 258     MISCREG_DATALO7,
 259
 260     MISCREG_TAGHI0 = 232,      //Bank 29: 232-239
 261     MISCREG_DATAHI1,
 262     MISCREG_TAGHI2,
 263     MISCREG_DATAHI3,
 264     MISCREG_TAGHI4,
 265     MISCREG_DATAHI5,
 266     MISCREG_TAGHI6,
 267     MISCREG_DATAHI7,
 268
 269
 270     MISCREG_ERROR_EPC = 240,    //Bank 30: 240-247
 271
 272     MISCREG_DESAVE = 248,       //Bank 31: 248-256
 273
 274     MISCREG_LLFLAG = 257,
 275     MISCREG_TP_VALUE,
 276
 277     MISCREG_NUMREGS
 278 };
 279
 280 const int NumMiscRegs = MISCREG_NUMREGS;
 281
 282 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
 283
 284 // Not applicable to MIPS
 285 using VecElem = ::DummyVecElem;
 286 using VecReg = ::DummyVecReg;
 287 using ConstVecReg = ::DummyConstVecReg;
 288 using VecRegContainer = ::DummyVecRegContainer;
 289 constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
 290 constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;
 291
 292 // Not applicable to MIPS
 293 using VecPredReg = ::DummyVecPredReg;
 294 using ConstVecPredReg = ::DummyConstVecPredReg;
 295 using VecPredRegContainer = ::DummyVecPredRegContainer;
 296 constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
 297 constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
 298
 299 } // namespace MipsISA
 300
 301 #endif