2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
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14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * Authors: Korey Sewell
32 #ifndef __ARCH_MIPS_REGISTERS_HH__
33 #define __ARCH_MIPS_REGISTERS_HH__
35 #include "arch/mips/generated/max_inst_regs.hh"
36 #include "base/misc.hh"
37 #include "base/types.hh"
44 using MipsISAInst::MaxInstSrcRegs;
45 using MipsISAInst::MaxInstDestRegs;
46 using MipsISAInst::MaxMiscDestRegs;
48 // Constants Related to the number of registers
49 const int NumIntArchRegs = 32;
50 const int NumIntSpecialRegs = 9;
51 const int NumFloatArchRegs = 32;
52 const int NumFloatSpecialRegs = 5;
54 const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
55 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs
56 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
58 const uint32_t MIPS32_QNAN = 0x7fbfffff;
59 const uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff);
61 enum FPControlRegNums {
62 FLOATREG_FIR = NumFloatArchRegs,
85 INTREG_LO = NumIntArchRegs,
86 INTREG_DSP_LO0 = INTREG_LO,
88 INTREG_DSP_HI0 = INTREG_HI,
102 // semantically meaningful register indices
103 const int ZeroReg = 0;
104 const int AssemblerReg = 1;
105 const int SyscallSuccessReg = 7;
106 const int FirstArgumentReg = 4;
107 const int ReturnValueReg = 2;
109 const int KernelReg0 = 26;
110 const int KernelReg1 = 27;
111 const int GlobalPointerReg = 28;
112 const int StackPointerReg = 29;
113 const int FramePointerReg = 30;
114 const int ReturnAddressReg = 31;
116 const int SyscallPseudoReturnReg = 3;
118 // Enumerate names for 'Control' Registers in the CPU
119 // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
120 // (Register Number-Register Select) Summary of Register
121 //------------------------------------------------------
122 // The first set of names classify the CP0 names as Register Banks
123 // for easy indexing when using the 'RD + SEL' index combination
124 // in CP0 instructions.
126 MISCREG_INDEX = 0, //Bank 0: 0 - 3
131 MISCREG_CP0_RANDOM = 8, //Bank 1: 8 - 15
136 MISCREG_VPE_SCHEDULE,
137 MISCREG_VPE_SCHEFBACK,
140 MISCREG_ENTRYLO0 = 16, //Bank 2: 16 - 23
147 MISCREG_TC_SCHEFBACK,
149 MISCREG_ENTRYLO1 = 24, // Bank 3: 24
151 MISCREG_CONTEXT = 32, // Bank 4: 32 - 33
152 MISCREG_CONTEXT_CONFIG,
154 MISCREG_PAGEMASK = 40, //Bank 5: 40 - 41
155 MISCREG_PAGEGRAIN = 41,
157 MISCREG_WIRED = 48, //Bank 6:48-55
164 MISCREG_HWRENA = 56, //Bank 7: 56-63
166 MISCREG_BADVADDR = 64, //Bank 8: 64-71
168 MISCREG_COUNT = 72, //Bank 9: 72-79
170 MISCREG_ENTRYHI = 80, //Bank 10: 80-87
172 MISCREG_COMPARE = 88, //Bank 11: 88-95
174 MISCREG_STATUS = 96, //Bank 12: 96-103
179 MISCREG_CAUSE = 104, //Bank 13: 104-111
181 MISCREG_EPC = 112, //Bank 14: 112-119
183 MISCREG_PRID = 120, //Bank 15: 120-127,
186 MISCREG_CONFIG = 128, //Bank 16: 128-135
196 MISCREG_LLADDR = 136, //Bank 17: 136-143
198 MISCREG_WATCHLO0 = 144, //Bank 18: 144-151
207 MISCREG_WATCHHI0 = 152, //Bank 19: 152-159
216 MISCREG_XCCONTEXT64 = 160, //Bank 20: 160-167
222 MISCREG_DEBUG = 184, //Bank 23: 184-191
223 MISCREG_TRACE_CONTROL1,
224 MISCREG_TRACE_CONTROL2,
225 MISCREG_USER_TRACE_DATA,
228 MISCREG_DEPC = 192, //Bank 24: 192-199
230 MISCREG_PERFCNT0 = 200, //Bank 25: 200-207
239 MISCREG_ERRCTL = 208, //Bank 26: 208-215
241 MISCREG_CACHEERR0 = 216, //Bank 27: 216-223
246 MISCREG_TAGLO0 = 224, //Bank 28: 224-231
255 MISCREG_TAGHI0 = 232, //Bank 29: 232-239
265 MISCREG_ERROR_EPC = 240, //Bank 30: 240-247
267 MISCREG_DESAVE = 248, //Bank 31: 248-256
269 MISCREG_LLFLAG = 257,
275 const int NumMiscRegs = MISCREG_NUMREGS;
277 // These help enumerate all the registers for dependence tracking.
278 const int FP_Base_DepTag = NumIntRegs;
279 const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
280 const int Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs;
282 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
284 typedef uint16_t RegIndex;
286 typedef uint32_t IntReg;
288 // floating point register file entry type
289 typedef uint32_t FloatRegBits;
290 typedef float FloatReg;
292 // cop-0/cop-1 system control register
293 typedef uint64_t MiscReg;
301 } // namespace MipsISA