src/arch/mips/stacktrace.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include "arch/mips/stacktrace.hh"
  30
  31 #include <string>
  32
  33 #include "arch/mips/isa_traits.hh"
  34 #include "base/bitfield.hh"
  35 #include "base/trace.hh"
  36 #include "cpu/base.hh"
  37 #include "cpu/thread_context.hh"
  38 #include "mem/port_proxy.hh"
  39 #include "sim/system.hh"
  40
  41 using namespace MipsISA;
  42
  43 StackTrace::StackTrace()
  44     : tc(0), stack(64)
  45 {
  46 }
  47
  48 StackTrace::StackTrace(ThreadContext *_tc, const StaticInstPtr &inst)
  49     : tc(0), stack(64)
  50 {
  51     trace(_tc, inst);
  52 }
  53
  54 StackTrace::~StackTrace()
  55 {
  56 }
  57
  58 void
  59 StackTrace::trace(ThreadContext *_tc, bool is_call)
  60 {
  61     tc = _tc;
  62     bool usermode = 0;
  63
  64     if (usermode) {
  65         stack.push_back(user);
  66         return;
  67     }
  68 }
  69
  70 bool
  71 StackTrace::isEntry(Addr addr)
  72 {
  73     return false;
  74 }
  75
  76 bool
  77 StackTrace::decodeStack(MachInst inst, int &disp)
  78 {
  79     // lda $sp, -disp($sp)
  80     //
  81     // Opcode<31:26> == 0x08
  82     // RA<25:21> == 30
  83     // RB<20:16> == 30
  84     // Disp<15:0>
  85     const MachInst mem_mask = 0xffff0000;
  86     const MachInst lda_pattern = 0x23de0000;
  87     const MachInst lda_disp_mask = 0x0000ffff;
  88
  89     // subq $sp, disp, $sp
  90     // addq $sp, disp, $sp
  91     //
  92     // Opcode<31:26> == 0x10
  93     // RA<25:21> == 30
  94     // Lit<20:13>
  95     // One<12> = 1
  96     // Func<11:5> == 0x20 (addq)
  97     // Func<11:5> == 0x29 (subq)
  98     // RC<4:0> == 30
  99     const MachInst intop_mask = 0xffe01fff;
 100     const MachInst addq_pattern = 0x43c0141e;
 101     const MachInst subq_pattern = 0x43c0153e;
 102     const MachInst intop_disp_mask = 0x001fe000;
 103     const int intop_disp_shift = 13;
 104
 105     if ((inst & mem_mask) == lda_pattern)
 106         disp = -sext<16>(inst & lda_disp_mask);
 107     else if ((inst & intop_mask) == addq_pattern)
 108         disp = -int((inst & intop_disp_mask) >> intop_disp_shift);
 109     else if ((inst & intop_mask) == subq_pattern)
 110         disp = int((inst & intop_disp_mask) >> intop_disp_shift);
 111     else
 112         return false;
 113
 114     return true;
 115 }
 116
 117 bool
 118 StackTrace::decodeSave(MachInst inst, int &reg, int &disp)
 119 {
 120     // lda $stq, disp($sp)
 121     //
 122     // Opcode<31:26> == 0x08
 123     // RA<25:21> == ?
 124     // RB<20:16> == 30
 125     // Disp<15:0>
 126     const MachInst stq_mask = 0xfc1f0000;
 127     const MachInst stq_pattern = 0xb41e0000;
 128     const MachInst stq_disp_mask = 0x0000ffff;
 129     const MachInst reg_mask = 0x03e00000;
 130     const int reg_shift = 21;
 131
 132     if ((inst & stq_mask) == stq_pattern) {
 133         reg = (inst & reg_mask) >> reg_shift;
 134         disp = sext<16>(inst & stq_disp_mask);
 135     } else {
 136         return false;
 137     }
 138
 139     return true;
 140 }
 141
 142 /*
 143  * Decode the function prologue for the function we're in, and note
 144  * which registers are stored where, and how large the stack frame is.
 145  */
 146 bool
 147 StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func,
 148                            int &size, Addr &ra)
 149 {
 150     size = 0;
 151     ra = 0;
 152
 153     for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) {
 154         MachInst inst = tc->getVirtProxy().read<MachInst>(pc);
 155
 156         int reg, disp;
 157         if (decodeStack(inst, disp)) {
 158             if (size) {
 159                 return true;
 160             }
 161             size += disp;
 162         } else if (decodeSave(inst, reg, disp)) {
 163             if (!ra && reg == ReturnAddressReg) {
 164                 ra = tc->getVirtProxy().read<Addr>(sp + disp);
 165                 if (!ra) {
 166                     return false;
 167                 }
 168             }
 169         }
 170     }
 171
 172     return true;
 173 }
 174
 175 #if TRACING_ON
 176 void
 177 StackTrace::dump()
 178 {
 179     panic("Stack trace dump not implemented.\n");
 180 }
 181 #endif