mips: Delete authors lists from mips files.
[gem5.git] / src / arch / mips / stacktrace.cc
1 /*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include "arch/mips/stacktrace.hh"
30
31 #include <string>
32
33 #include "arch/mips/isa_traits.hh"
34 #include "arch/mips/vtophys.hh"
35 #include "base/bitfield.hh"
36 #include "base/trace.hh"
37 #include "cpu/base.hh"
38 #include "cpu/thread_context.hh"
39 #include "mem/fs_translating_port_proxy.hh"
40 #include "sim/system.hh"
41
42 using namespace MipsISA;
43
44 ProcessInfo::ProcessInfo(ThreadContext *_tc) : tc(_tc)
45 {}
46
47 Addr
48 ProcessInfo::task(Addr ksp) const
49 {
50 Addr base = ksp & ~0x3fff;
51 if (base == ULL(0xfffffc0000000000))
52 return 0;
53
54 Addr tsk;
55
56 PortProxy &vp = tc->getVirtProxy();
57 tsk = vp.read<Addr>(base + task_off, GuestByteOrder);
58
59 return tsk;
60 }
61
62 int
63 ProcessInfo::pid(Addr ksp) const
64 {
65 Addr task = this->task(ksp);
66 if (!task)
67 return -1;
68
69 uint16_t pd;
70
71 PortProxy &vp = tc->getVirtProxy();
72 pd = vp.read<uint16_t>(task + pid_off, GuestByteOrder);
73
74 return pd;
75 }
76
77 std::string
78 ProcessInfo::name(Addr ksp) const
79 {
80 Addr task = this->task(ksp);
81 if (!task)
82 return "console";
83
84 char comm[256];
85 tc->getVirtProxy().readString(comm, task + name_off, sizeof(comm));
86 if (!comm[0])
87 return "startup";
88
89 return comm;
90 }
91
92 StackTrace::StackTrace()
93 : tc(0), stack(64)
94 {
95 }
96
97 StackTrace::StackTrace(ThreadContext *_tc, const StaticInstPtr &inst)
98 : tc(0), stack(64)
99 {
100 trace(_tc, inst);
101 }
102
103 StackTrace::~StackTrace()
104 {
105 }
106
107 void
108 StackTrace::trace(ThreadContext *_tc, bool is_call)
109 {
110 tc = _tc;
111 bool usermode = 0;
112
113 if (usermode) {
114 stack.push_back(user);
115 return;
116 }
117 }
118
119 bool
120 StackTrace::isEntry(Addr addr)
121 {
122 return false;
123 }
124
125 bool
126 StackTrace::decodeStack(MachInst inst, int &disp)
127 {
128 // lda $sp, -disp($sp)
129 //
130 // Opcode<31:26> == 0x08
131 // RA<25:21> == 30
132 // RB<20:16> == 30
133 // Disp<15:0>
134 const MachInst mem_mask = 0xffff0000;
135 const MachInst lda_pattern = 0x23de0000;
136 const MachInst lda_disp_mask = 0x0000ffff;
137
138 // subq $sp, disp, $sp
139 // addq $sp, disp, $sp
140 //
141 // Opcode<31:26> == 0x10
142 // RA<25:21> == 30
143 // Lit<20:13>
144 // One<12> = 1
145 // Func<11:5> == 0x20 (addq)
146 // Func<11:5> == 0x29 (subq)
147 // RC<4:0> == 30
148 const MachInst intop_mask = 0xffe01fff;
149 const MachInst addq_pattern = 0x43c0141e;
150 const MachInst subq_pattern = 0x43c0153e;
151 const MachInst intop_disp_mask = 0x001fe000;
152 const int intop_disp_shift = 13;
153
154 if ((inst & mem_mask) == lda_pattern)
155 disp = -sext<16>(inst & lda_disp_mask);
156 else if ((inst & intop_mask) == addq_pattern)
157 disp = -int((inst & intop_disp_mask) >> intop_disp_shift);
158 else if ((inst & intop_mask) == subq_pattern)
159 disp = int((inst & intop_disp_mask) >> intop_disp_shift);
160 else
161 return false;
162
163 return true;
164 }
165
166 bool
167 StackTrace::decodeSave(MachInst inst, int &reg, int &disp)
168 {
169 // lda $stq, disp($sp)
170 //
171 // Opcode<31:26> == 0x08
172 // RA<25:21> == ?
173 // RB<20:16> == 30
174 // Disp<15:0>
175 const MachInst stq_mask = 0xfc1f0000;
176 const MachInst stq_pattern = 0xb41e0000;
177 const MachInst stq_disp_mask = 0x0000ffff;
178 const MachInst reg_mask = 0x03e00000;
179 const int reg_shift = 21;
180
181 if ((inst & stq_mask) == stq_pattern) {
182 reg = (inst & reg_mask) >> reg_shift;
183 disp = sext<16>(inst & stq_disp_mask);
184 } else {
185 return false;
186 }
187
188 return true;
189 }
190
191 /*
192 * Decode the function prologue for the function we're in, and note
193 * which registers are stored where, and how large the stack frame is.
194 */
195 bool
196 StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func,
197 int &size, Addr &ra)
198 {
199 size = 0;
200 ra = 0;
201
202 for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) {
203 MachInst inst = tc->getVirtProxy().read<MachInst>(pc);
204
205 int reg, disp;
206 if (decodeStack(inst, disp)) {
207 if (size) {
208 return true;
209 }
210 size += disp;
211 } else if (decodeSave(inst, reg, disp)) {
212 if (!ra && reg == ReturnAddressReg) {
213 ra = tc->getVirtProxy().read<Addr>(sp + disp);
214 if (!ra) {
215 return false;
216 }
217 }
218 }
219 }
220
221 return true;
222 }
223
224 #if TRACING_ON
225 void
226 StackTrace::dump()
227 {
228 panic("Stack trace dump not implemented.\n");
229 }
230 #endif