2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * Authors: Nathan Binkert
37 #include "arch/mips/pra_constants.hh"
38 #include "arch/mips/pagetable.hh"
39 #include "arch/mips/tlb.hh"
40 #include "arch/mips/faults.hh"
41 #include "arch/mips/utility.hh"
42 #include "base/inifile.hh"
43 #include "base/str.hh"
44 #include "base/trace.hh"
45 #include "cpu/thread_context.hh"
46 #include "sim/process.hh"
47 #include "mem/page_table.hh"
48 #include "params/MipsDTB.hh"
49 #include "params/MipsITB.hh"
50 #include "params/MipsTLB.hh"
51 #include "params/MipsUTB.hh"
55 using namespace MipsISA
;
57 ///////////////////////////////////////////////////////////////////////
62 #define MODE2MASK(X) (1 << (X))
64 TLB::TLB(const Params
*p
)
65 : BaseTLB(p
), size(p
->size
), nlu(0)
67 table
= new MipsISA::PTE
[size
];
68 memset(table
, 0, sizeof(MipsISA::PTE
[size
]));
78 // look up an entry in the TLB
80 TLB::lookup(Addr vpn
, uint8_t asn
) const
82 // assume not found...
83 MipsISA::PTE
*retval
= NULL
;
84 PageTable::const_iterator i
= lookupTable
.find(vpn
);
85 if (i
!= lookupTable
.end()) {
86 while (i
->first
== vpn
) {
87 int index
= i
->second
;
88 MipsISA::PTE
*pte
= &table
[index
];
90 /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
91 Addr Mask
= pte
->Mask
;
94 // warn("Valid: %d - %d\n",pte->V0,pte->V1);
95 if(((vpn
& InvMask
) == (VPN
& InvMask
)) && (pte
->G
|| (asn
== pte
->asid
)))
96 { // We have a VPN + ASID Match
104 DPRINTF(TLB
, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn
, (int)asn
,
105 retval
? "hit" : "miss", retval
? retval
->PFN1
: 0);
109 MipsISA::PTE
* TLB::getEntry(unsigned Index
) const
111 // Make sure that Index is valid
113 return &table
[Index
];
116 int TLB::probeEntry(Addr vpn
,uint8_t asn
) const
118 // assume not found...
119 MipsISA::PTE
*retval
= NULL
;
121 PageTable::const_iterator i
= lookupTable
.find(vpn
);
122 if (i
!= lookupTable
.end()) {
123 while (i
->first
== vpn
) {
124 int index
= i
->second
;
125 MipsISA::PTE
*pte
= &table
[index
];
127 /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
128 Addr Mask
= pte
->Mask
;
129 Addr InvMask
= ~Mask
;
131 if(((vpn
& InvMask
) == (VPN
& InvMask
)) && (pte
->G
|| (asn
== pte
->asid
)))
132 { // We have a VPN + ASID Match
141 DPRINTF(MipsPRA
,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn
,asn
,Ind
);
145 TLB::checkCacheability(RequestPtr
&req
)
147 Addr VAddrUncacheable
= 0xA0000000;
148 // In MIPS, cacheability is controlled by certain bits of the virtual address
149 // or by the TLB entry
150 if((req
->getVaddr() & VAddrUncacheable
) == VAddrUncacheable
) {
151 // mark request as uncacheable
152 req
->setFlags(Request::UNCACHEABLE
);
156 void TLB::insertAt(MipsISA::PTE
&pte
, unsigned Index
, int _smallPages
)
158 smallPages
=_smallPages
;
160 warn("Attempted to write at index (%d) beyond TLB size (%d)",Index
,size
);
163 DPRINTF(TLB
,"TLB[%d]: %x %x %x %x\n",Index
,pte
.Mask
<<11,((pte
.VPN
<< 11) | pte
.asid
),((pte
.PFN0
<<6) | (pte
.C0
<< 3) | (pte
.D0
<< 2) | (pte
.V0
<<1) | pte
.G
),
164 ((pte
.PFN1
<<6) | (pte
.C1
<< 3) | (pte
.D1
<< 2) | (pte
.V1
<<1) | pte
.G
));
165 if(table
[Index
].V0
== true || table
[Index
].V1
== true){ // Previous entry is valid
166 PageTable::iterator i
= lookupTable
.find(table
[Index
].VPN
);
167 lookupTable
.erase(i
);
170 // Update fast lookup table
171 lookupTable
.insert(make_pair(table
[Index
].VPN
, Index
));
172 // int TestIndex=probeEntry(pte.VPN,pte.asid);
173 // warn("Inserted at: %d, Found at: %d (%x)\n",Index,TestIndex,pte.Mask);
178 // insert a new TLB entry
180 TLB::insert(Addr addr
, MipsISA::PTE
&pte
)
182 fatal("TLB Insert not yet implemented\n");
185 /* MipsISA::VAddr vaddr = addr;
186 if (table[nlu].valid) {
187 Addr oldvpn = table[nlu].tag;
188 PageTable::iterator i = lookupTable.find(oldvpn);
190 if (i == lookupTable.end())
191 panic("TLB entry not found in lookupTable");
194 while ((index = i->second) != nlu) {
195 if (table[index].tag != oldvpn)
196 panic("TLB entry not found in lookupTable");
201 DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn);
203 lookupTable.erase(i);
206 DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn);
209 table[nlu].tag = vaddr.vpn();
210 table[nlu].valid = true;
212 lookupTable.insert(make_pair(vaddr.vpn(), nlu));
220 DPRINTF(TLB
, "flushAll\n");
221 memset(table
, 0, sizeof(MipsISA::PTE
[size
]));
227 TLB::serialize(ostream
&os
)
229 SERIALIZE_SCALAR(size
);
230 SERIALIZE_SCALAR(nlu
);
232 for (int i
= 0; i
< size
; i
++) {
233 nameOut(os
, csprintf("%s.PTE%d", name(), i
));
234 table
[i
].serialize(os
);
239 TLB::unserialize(Checkpoint
*cp
, const string
§ion
)
241 UNSERIALIZE_SCALAR(size
);
242 UNSERIALIZE_SCALAR(nlu
);
244 for (int i
= 0; i
< size
; i
++) {
245 table
[i
].unserialize(cp
, csprintf("%s.PTE%d", section
, i
));
246 if (table
[i
].V0
|| table
[i
].V1
) {
247 lookupTable
.insert(make_pair(table
[i
].VPN
, i
));
256 .name(name() + ".read_hits")
257 .desc("DTB read hits")
261 .name(name() + ".read_misses")
262 .desc("DTB read misses")
267 .name(name() + ".read_accesses")
268 .desc("DTB read accesses")
272 .name(name() + ".write_hits")
273 .desc("DTB write hits")
277 .name(name() + ".write_misses")
278 .desc("DTB write misses")
283 .name(name() + ".write_accesses")
284 .desc("DTB write accesses")
288 .name(name() + ".hits")
293 .name(name() + ".misses")
298 .name(name() + ".invalids")
299 .desc("DTB access violations")
303 .name(name() + ".accesses")
304 .desc("DTB accesses")
307 hits
= read_hits
+ write_hits
;
308 misses
= read_misses
+ write_misses
;
309 accesses
= read_accesses
+ write_accesses
;
313 ITB::translateAtomic(RequestPtr req
, ThreadContext
*tc
)
316 Process
* p
= tc
->getProcessPtr();
318 Fault fault
= p
->pTable
->translate(req
);
324 if(MipsISA::IsKSeg0(req
->getVaddr()))
326 // Address will not be translated through TLB, set response, and go!
327 req
->setPaddr(MipsISA::KSeg02Phys(req
->getVaddr()));
328 if(MipsISA::getOperatingMode(tc
->readMiscReg(MipsISA::Status
)) != mode_kernel
|| req
->isMisaligned())
330 AddressErrorFault
*Flt
= new AddressErrorFault();
331 /* BadVAddr must be set */
332 Flt
->BadVAddr
= req
->getVaddr();
336 else if(MipsISA::IsKSeg1(req
->getVaddr()))
338 // Address will not be translated through TLB, set response, and go!
339 req
->setPaddr(MipsISA::KSeg02Phys(req
->getVaddr()));
343 /* This is an optimization - smallPages is updated every time a TLB operation is performed
344 That way, we don't need to look at Config3 _ SP and PageGrain _ ESP every time we
348 VPN
=((req
->getVaddr() >> 11));
350 VPN
=((req
->getVaddr() >> 11) & 0xFFFFFFFC);
352 uint8_t Asid
= req
->getAsid();
353 if(req
->isMisaligned()){ // Unaligned address!
354 AddressErrorFault
*Flt
= new AddressErrorFault();
355 /* BadVAddr must be set */
356 Flt
->BadVAddr
= req
->getVaddr();
359 MipsISA::PTE
*pte
= lookup(VPN
,Asid
);
361 {// Ok, found something
362 /* Check for valid bits */
365 if((((req
->getVaddr()) >> pte
->AddrShiftAmount
) & 1) ==0){
377 ItbInvalidFault
*Flt
= new ItbInvalidFault();
378 /* EntryHi VPN, ASID fields must be set */
379 Flt
->EntryHi_Asid
= Asid
;
380 Flt
->EntryHi_VPN2
= (VPN
>>2);
381 Flt
->EntryHi_VPN2X
= (VPN
& 0x3);
383 /* BadVAddr must be set */
384 Flt
->BadVAddr
= req
->getVaddr();
386 /* Context must be set */
387 Flt
->Context_BadVPN2
= (VPN
>> 2);
391 {// Ok, this is really a match, set paddr
399 PAddr
>>= (pte
->AddrShiftAmount
-12);
400 PAddr
<<= pte
->AddrShiftAmount
;
401 PAddr
|= ((req
->getVaddr()) & pte
->OffsetMask
);
402 req
->setPaddr(PAddr
);
408 { // Didn't find any match, return a TLB Refill Exception
410 ItbRefillFault
*Flt
=new ItbRefillFault();
411 /* EntryHi VPN, ASID fields must be set */
412 Flt
->EntryHi_Asid
= Asid
;
413 Flt
->EntryHi_VPN2
= (VPN
>>2);
414 Flt
->EntryHi_VPN2X
= (VPN
& 0x3);
417 /* BadVAddr must be set */
418 Flt
->BadVAddr
= req
->getVaddr();
420 /* Context must be set */
421 Flt
->Context_BadVPN2
= (VPN
>> 2);
425 return checkCacheability(req
);
430 ITB::translateTiming(RequestPtr req
, ThreadContext
*tc
,
431 Translation
*translation
)
434 translation
->finish(translateAtomic(req
, tc
), req
, tc
, false);
438 DTB::translateAtomic(RequestPtr req
, ThreadContext
*tc
, bool write
)
441 Process
* p
= tc
->getProcessPtr();
443 Fault fault
= p
->pTable
->translate(req
);
449 if(MipsISA::IsKSeg0(req
->getVaddr()))
451 // Address will not be translated through TLB, set response, and go!
452 req
->setPaddr(MipsISA::KSeg02Phys(req
->getVaddr()));
453 if(MipsISA::getOperatingMode(tc
->readMiscReg(MipsISA::Status
)) != mode_kernel
|| req
->isMisaligned())
455 StoreAddressErrorFault
*Flt
= new StoreAddressErrorFault();
456 /* BadVAddr must be set */
457 Flt
->BadVAddr
= req
->getVaddr();
462 else if(MipsISA::IsKSeg1(req
->getVaddr()))
464 // Address will not be translated through TLB, set response, and go!
465 req
->setPaddr(MipsISA::KSeg02Phys(req
->getVaddr()));
469 /* This is an optimization - smallPages is updated every time a TLB operation is performed
470 That way, we don't need to look at Config3 _ SP and PageGrain _ ESP every time we
472 Addr VPN
=((req
->getVaddr() >> 11) & 0xFFFFFFFC);
474 VPN
=((req
->getVaddr() >> 11));
476 uint8_t Asid
= req
->getAsid();
477 MipsISA::PTE
*pte
= lookup(VPN
,Asid
);
478 if(req
->isMisaligned()){ // Unaligned address!
479 StoreAddressErrorFault
*Flt
= new StoreAddressErrorFault();
480 /* BadVAddr must be set */
481 Flt
->BadVAddr
= req
->getVaddr();
485 {// Ok, found something
486 /* Check for valid bits */
490 if(((((req
->getVaddr()) >> pte
->AddrShiftAmount
) & 1)) ==0){
506 DtbInvalidFault
*Flt
= new DtbInvalidFault();
507 /* EntryHi VPN, ASID fields must be set */
508 Flt
->EntryHi_Asid
= Asid
;
509 Flt
->EntryHi_VPN2
= (VPN
>>2);
510 Flt
->EntryHi_VPN2X
= (VPN
& 0x3);
513 /* BadVAddr must be set */
514 Flt
->BadVAddr
= req
->getVaddr();
516 /* Context must be set */
517 Flt
->Context_BadVPN2
= (VPN
>> 2);
522 {// Ok, this is really a match, set paddr
526 TLBModifiedFault
*Flt
= new TLBModifiedFault();
527 /* EntryHi VPN, ASID fields must be set */
528 Flt
->EntryHi_Asid
= Asid
;
529 Flt
->EntryHi_VPN2
= (VPN
>>2);
530 Flt
->EntryHi_VPN2X
= (VPN
& 0x3);
533 /* BadVAddr must be set */
534 Flt
->BadVAddr
= req
->getVaddr();
536 /* Context must be set */
537 Flt
->Context_BadVPN2
= (VPN
>> 2);
547 PAddr
>>= (pte
->AddrShiftAmount
-12);
548 PAddr
<<= pte
->AddrShiftAmount
;
549 PAddr
|= ((req
->getVaddr()) & pte
->OffsetMask
);
550 req
->setPaddr(PAddr
);
554 { // Didn't find any match, return a TLB Refill Exception
556 DtbRefillFault
*Flt
=new DtbRefillFault();
557 /* EntryHi VPN, ASID fields must be set */
558 Flt
->EntryHi_Asid
= Asid
;
559 Flt
->EntryHi_VPN2
= (VPN
>>2);
560 Flt
->EntryHi_VPN2X
= (VPN
& 0x3);
563 /* BadVAddr must be set */
564 Flt
->BadVAddr
= req
->getVaddr();
566 /* Context must be set */
567 Flt
->Context_BadVPN2
= (VPN
>> 2);
571 return checkCacheability(req
);
576 DTB::translateTiming(RequestPtr req
, ThreadContext
*tc
,
577 Translation
*translation
, bool write
)
580 translation
->finish(translateAtomic(req
, tc
, write
), req
, tc
, write
);
583 ///////////////////////////////////////////////////////////////////////
587 ITB::ITB(const Params
*p
)
595 // /* hits - causes failure for some reason
596 // .name(name() + ".hits")
597 // .desc("ITB hits");
599 // .name(name() + ".misses")
600 // .desc("ITB misses");
602 // .name(name() + ".acv")
605 // .name(name() + ".accesses")
606 // .desc("ITB accesses");
608 // accesses = hits + misses + invalids; */
613 ///////////////////////////////////////////////////////////////////////
617 DTB::DTB(const Params
*p
)
621 ///////////////////////////////////////////////////////////////////////
625 UTB::UTB(const Params
*p
)
632 TLB::index(bool advance
)
634 MipsISA::PTE
*pte
= &table
[nlu
];
643 MipsITBParams::create()
645 return new MipsISA::ITB(this);
649 MipsDTBParams::create()
651 return new MipsISA::DTB(this);
655 MipsUTBParams::create()
657 return new MipsISA::UTB(this);