2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * Authors: Nathan Binkert
37 #include "arch/mips/pra_constants.hh"
38 #include "arch/mips/pagetable.hh"
39 #include "arch/mips/tlb.hh"
40 #include "arch/mips/faults.hh"
41 #include "arch/mips/utility.hh"
42 #include "base/inifile.hh"
43 #include "base/str.hh"
44 #include "base/trace.hh"
45 #include "cpu/thread_context.hh"
46 #include "sim/process.hh"
47 #include "mem/page_table.hh"
48 #include "params/MipsTLB.hh"
51 using namespace MipsISA
;
53 ///////////////////////////////////////////////////////////////////////
58 static inline mode_type
59 getOperatingMode(MiscReg Stat
)
61 if ((Stat
& 0x10000006) != 0 || (Stat
& 0x18) ==0) {
63 } else if ((Stat
& 0x18) == 0x8) {
64 return mode_supervisor
;
65 } else if ((Stat
& 0x18) == 0x10) {
73 TLB::TLB(const Params
*p
)
74 : BaseTLB(p
), size(p
->size
), nlu(0)
76 table
= new PTE
[size
];
77 memset(table
, 0, sizeof(PTE
[size
]));
87 // look up an entry in the TLB
89 TLB::lookup(Addr vpn
, uint8_t asn
) const
91 // assume not found...
93 PageTable::const_iterator i
= lookupTable
.find(vpn
);
94 if (i
!= lookupTable
.end()) {
95 while (i
->first
== vpn
) {
96 int index
= i
->second
;
97 PTE
*pte
= &table
[index
];
99 /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
100 Addr Mask
= pte
->Mask
;
101 Addr InvMask
= ~Mask
;
103 if (((vpn
& InvMask
) == (VPN
& InvMask
)) &&
104 (pte
->G
|| (asn
== pte
->asid
))) {
105 // We have a VPN + ASID Match
113 DPRINTF(TLB
, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn
, (int)asn
,
114 retval
? "hit" : "miss", retval
? retval
->PFN1
: 0);
119 TLB::getEntry(unsigned Index
) const
121 // Make sure that Index is valid
123 return &table
[Index
];
127 TLB::probeEntry(Addr vpn
, uint8_t asn
) const
129 // assume not found...
132 PageTable::const_iterator i
= lookupTable
.find(vpn
);
133 if (i
!= lookupTable
.end()) {
134 while (i
->first
== vpn
) {
135 int index
= i
->second
;
136 PTE
*pte
= &table
[index
];
138 /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
139 Addr Mask
= pte
->Mask
;
140 Addr InvMask
= ~Mask
;
142 if (((vpn
& InvMask
) == (VPN
& InvMask
)) &&
143 (pte
->G
|| (asn
== pte
->asid
))) {
144 // We have a VPN + ASID Match
152 DPRINTF(MipsPRA
,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn
,asn
,Ind
);
157 TLB::checkCacheability(RequestPtr
&req
)
159 Addr VAddrUncacheable
= 0xA0000000;
160 // In MIPS, cacheability is controlled by certain bits of the virtual
161 // address or by the TLB entry
162 if ((req
->getVaddr() & VAddrUncacheable
) == VAddrUncacheable
) {
163 // mark request as uncacheable
164 req
->setFlags(Request::UNCACHEABLE
);
170 TLB::insertAt(PTE
&pte
, unsigned Index
, int _smallPages
)
172 smallPages
= _smallPages
;
174 warn("Attempted to write at index (%d) beyond TLB size (%d)",
178 DPRINTF(TLB
, "TLB[%d]: %x %x %x %x\n",
179 Index
, pte
.Mask
<< 11,
180 ((pte
.VPN
<< 11) | pte
.asid
),
181 ((pte
.PFN0
<< 6) | (pte
.C0
<< 3) |
182 (pte
.D0
<< 2) | (pte
.V0
<<1) | pte
.G
),
183 ((pte
.PFN1
<<6) | (pte
.C1
<< 3) |
184 (pte
.D1
<< 2) | (pte
.V1
<<1) | pte
.G
));
185 if (table
[Index
].V0
== true || table
[Index
].V1
== true) {
186 // Previous entry is valid
187 PageTable::iterator i
= lookupTable
.find(table
[Index
].VPN
);
188 lookupTable
.erase(i
);
191 // Update fast lookup table
192 lookupTable
.insert(make_pair(table
[Index
].VPN
, Index
));
196 // insert a new TLB entry
198 TLB::insert(Addr addr
, PTE
&pte
)
200 fatal("TLB Insert not yet implemented\n");
206 DPRINTF(TLB
, "flushAll\n");
207 memset(table
, 0, sizeof(PTE
[size
]));
213 TLB::serialize(ostream
&os
)
215 SERIALIZE_SCALAR(size
);
216 SERIALIZE_SCALAR(nlu
);
218 for (int i
= 0; i
< size
; i
++) {
219 nameOut(os
, csprintf("%s.PTE%d", name(), i
));
220 table
[i
].serialize(os
);
225 TLB::unserialize(Checkpoint
*cp
, const string
§ion
)
227 UNSERIALIZE_SCALAR(size
);
228 UNSERIALIZE_SCALAR(nlu
);
230 for (int i
= 0; i
< size
; i
++) {
231 table
[i
].unserialize(cp
, csprintf("%s.PTE%d", section
, i
));
232 if (table
[i
].V0
|| table
[i
].V1
) {
233 lookupTable
.insert(make_pair(table
[i
].VPN
, i
));
242 .name(name() + ".read_hits")
243 .desc("DTB read hits")
247 .name(name() + ".read_misses")
248 .desc("DTB read misses")
253 .name(name() + ".read_accesses")
254 .desc("DTB read accesses")
258 .name(name() + ".write_hits")
259 .desc("DTB write hits")
263 .name(name() + ".write_misses")
264 .desc("DTB write misses")
269 .name(name() + ".write_accesses")
270 .desc("DTB write accesses")
274 .name(name() + ".hits")
279 .name(name() + ".misses")
284 .name(name() + ".accesses")
285 .desc("DTB accesses")
288 hits
= read_hits
+ write_hits
;
289 misses
= read_misses
+ write_misses
;
290 accesses
= read_accesses
+ write_accesses
;
294 TLB::translateInst(RequestPtr req
, ThreadContext
*tc
)
297 Process
* p
= tc
->getProcessPtr();
299 Fault fault
= p
->pTable
->translate(req
);
300 if (fault
!= NoFault
)
305 if (IsKSeg0(req
->getVaddr())) {
306 // Address will not be translated through TLB, set response, and go!
307 req
->setPaddr(KSeg02Phys(req
->getVaddr()));
308 if (getOperatingMode(tc
->readMiscReg(MISCREG_STATUS
)) != mode_kernel
||
309 req
->isMisaligned()) {
310 AddressErrorFault
*Flt
= new AddressErrorFault();
311 /* BadVAddr must be set */
312 Flt
->badVAddr
= req
->getVaddr();
315 } else if(IsKSeg1(req
->getVaddr())) {
316 // Address will not be translated through TLB, set response, and go!
317 req
->setPaddr(KSeg02Phys(req
->getVaddr()));
320 * This is an optimization - smallPages is updated every time a TLB
321 * operation is performed. That way, we don't need to look at
322 * Config3 _ SP and PageGrain _ ESP every time we do a TLB lookup
325 if (smallPages
== 1) {
326 VPN
= ((req
->getVaddr() >> 11));
328 VPN
= ((req
->getVaddr() >> 11) & 0xFFFFFFFC);
330 uint8_t Asid
= req
->getAsid();
331 if (req
->isMisaligned()) {
332 // Unaligned address!
333 AddressErrorFault
*Flt
= new AddressErrorFault();
334 /* BadVAddr must be set */
335 Flt
->badVAddr
= req
->getVaddr();
338 PTE
*pte
= lookup(VPN
,Asid
);
340 // Ok, found something
341 /* Check for valid bits */
344 if ((((req
->getVaddr()) >> pte
->AddrShiftAmount
) & 1) == 0) {
354 if (Valid
== false) {
356 ItbInvalidFault
*Flt
= new ItbInvalidFault();
357 /* EntryHi VPN, ASID fields must be set */
358 Flt
->entryHiAsid
= Asid
;
359 Flt
->entryHiVPN2
= (VPN
>> 2);
360 Flt
->entryHiVPN2X
= (VPN
& 0x3);
362 /* BadVAddr must be set */
363 Flt
->badVAddr
= req
->getVaddr();
365 /* Context must be set */
366 Flt
->contextBadVPN2
= (VPN
>> 2);
369 // Ok, this is really a match, set paddr
376 PAddr
>>= (pte
->AddrShiftAmount
- 12);
377 PAddr
<<= pte
->AddrShiftAmount
;
378 PAddr
|= ((req
->getVaddr()) & pte
->OffsetMask
);
379 req
->setPaddr(PAddr
);
382 // Didn't find any match, return a TLB Refill Exception
383 ItbRefillFault
*Flt
= new ItbRefillFault();
384 /* EntryHi VPN, ASID fields must be set */
385 Flt
->entryHiAsid
= Asid
;
386 Flt
->entryHiVPN2
= (VPN
>> 2);
387 Flt
->entryHiVPN2X
= (VPN
& 0x3);
389 /* BadVAddr must be set */
390 Flt
->badVAddr
= req
->getVaddr();
392 /* Context must be set */
393 Flt
->contextBadVPN2
= (VPN
>> 2);
397 return checkCacheability(req
);
402 TLB::translateData(RequestPtr req
, ThreadContext
*tc
, bool write
)
405 //@TODO: This should actually use TLB instead of going directly
406 // to the page table in syscall mode.
408 * Check for alignment faults
410 if (req
->getVaddr() & (req
->getSize() - 1)) {
411 DPRINTF(TLB
, "Alignment Fault on %#x, size = %d", req
->getVaddr(),
413 return new AlignmentFault();
417 Process
* p
= tc
->getProcessPtr();
419 Fault fault
= p
->pTable
->translate(req
);
420 if (fault
!= NoFault
)
425 if (IsKSeg0(req
->getVaddr())) {
426 // Address will not be translated through TLB, set response, and go!
427 req
->setPaddr(KSeg02Phys(req
->getVaddr()));
428 if (getOperatingMode(tc
->readMiscReg(MISCREG_STATUS
)) != mode_kernel
||
429 req
->isMisaligned()) {
430 StoreAddressErrorFault
*Flt
= new StoreAddressErrorFault();
431 /* BadVAddr must be set */
432 Flt
->badVAddr
= req
->getVaddr();
436 } else if(IsKSeg1(req
->getVaddr())) {
437 // Address will not be translated through TLB, set response, and go!
438 req
->setPaddr(KSeg02Phys(req
->getVaddr()));
441 * This is an optimization - smallPages is updated every time a TLB
442 * operation is performed. That way, we don't need to look at
443 * Config3 _ SP and PageGrain _ ESP every time we do a TLB lookup
445 Addr VPN
= ((req
->getVaddr() >> 11) & 0xFFFFFFFC);
446 if (smallPages
== 1) {
447 VPN
= ((req
->getVaddr() >> 11));
449 uint8_t Asid
= req
->getAsid();
450 PTE
*pte
= lookup(VPN
, Asid
);
451 if (req
->isMisaligned()) {
452 // Unaligned address!
453 StoreAddressErrorFault
*Flt
= new StoreAddressErrorFault();
454 /* BadVAddr must be set */
455 Flt
->badVAddr
= req
->getVaddr();
459 // Ok, found something
460 /* Check for valid bits */
464 if (((((req
->getVaddr()) >> pte
->AddrShiftAmount
) & 1)) == 0) {
476 if (Valid
== false) {
478 DtbInvalidFault
*Flt
= new DtbInvalidFault();
479 /* EntryHi VPN, ASID fields must be set */
480 Flt
->entryHiAsid
= Asid
;
481 Flt
->entryHiVPN2
= (VPN
>>2);
482 Flt
->entryHiVPN2X
= (VPN
& 0x3);
484 /* BadVAddr must be set */
485 Flt
->badVAddr
= req
->getVaddr();
487 /* Context must be set */
488 Flt
->contextBadVPN2
= (VPN
>> 2);
492 // Ok, this is really a match, set paddr
494 TLBModifiedFault
*Flt
= new TLBModifiedFault();
495 /* EntryHi VPN, ASID fields must be set */
496 Flt
->entryHiAsid
= Asid
;
497 Flt
->entryHiVPN2
= (VPN
>> 2);
498 Flt
->entryHiVPN2X
= (VPN
& 0x3);
500 /* BadVAddr must be set */
501 Flt
->badVAddr
= req
->getVaddr();
503 /* Context must be set */
504 Flt
->contextBadVPN2
= (VPN
>> 2);
513 PAddr
>>= (pte
->AddrShiftAmount
- 12);
514 PAddr
<<= pte
->AddrShiftAmount
;
515 PAddr
|= ((req
->getVaddr()) & pte
->OffsetMask
);
516 req
->setPaddr(PAddr
);
519 // Didn't find any match, return a TLB Refill Exception
520 DtbRefillFault
*Flt
= new DtbRefillFault();
521 /* EntryHi VPN, ASID fields must be set */
522 Flt
->entryHiAsid
= Asid
;
523 Flt
->entryHiVPN2
= (VPN
>> 2);
524 Flt
->entryHiVPN2X
= (VPN
& 0x3);
526 /* BadVAddr must be set */
527 Flt
->badVAddr
= req
->getVaddr();
529 /* Context must be set */
530 Flt
->contextBadVPN2
= (VPN
>> 2);
534 return checkCacheability(req
);
539 TLB::translateAtomic(RequestPtr req
, ThreadContext
*tc
, Mode mode
)
542 return translateInst(req
, tc
);
544 return translateData(req
, tc
, mode
== Write
);
548 TLB::translateTiming(RequestPtr req
, ThreadContext
*tc
,
549 Translation
*translation
, Mode mode
)
552 translation
->finish(translateAtomic(req
, tc
, mode
), req
, tc
, mode
);
557 TLB::index(bool advance
)
559 PTE
*pte
= &table
[nlu
];
568 MipsTLBParams::create()
570 return new TLB(this);