2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * Authors: Nathan Binkert
37 #include "arch/mips/pra_constants.hh"
38 #include "arch/mips/pagetable.hh"
39 #include "arch/mips/tlb.hh"
40 #include "arch/mips/faults.hh"
41 #include "arch/mips/utility.hh"
42 #include "base/inifile.hh"
43 #include "base/str.hh"
44 #include "base/trace.hh"
45 #include "cpu/thread_context.hh"
46 #include "sim/process.hh"
47 #include "mem/page_table.hh"
48 #include "params/MipsTLB.hh"
52 using namespace MipsISA
;
54 ///////////////////////////////////////////////////////////////////////
59 #define MODE2MASK(X) (1 << (X))
61 TLB::TLB(const Params
*p
)
62 : BaseTLB(p
), size(p
->size
), nlu(0)
64 table
= new MipsISA::PTE
[size
];
65 memset(table
, 0, sizeof(MipsISA::PTE
[size
]));
75 // look up an entry in the TLB
77 TLB::lookup(Addr vpn
, uint8_t asn
) const
79 // assume not found...
80 MipsISA::PTE
*retval
= NULL
;
81 PageTable::const_iterator i
= lookupTable
.find(vpn
);
82 if (i
!= lookupTable
.end()) {
83 while (i
->first
== vpn
) {
84 int index
= i
->second
;
85 MipsISA::PTE
*pte
= &table
[index
];
87 /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
88 Addr Mask
= pte
->Mask
;
91 // warn("Valid: %d - %d\n",pte->V0,pte->V1);
92 if(((vpn
& InvMask
) == (VPN
& InvMask
)) && (pte
->G
|| (asn
== pte
->asid
)))
93 { // We have a VPN + ASID Match
101 DPRINTF(TLB
, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn
, (int)asn
,
102 retval
? "hit" : "miss", retval
? retval
->PFN1
: 0);
106 MipsISA::PTE
* TLB::getEntry(unsigned Index
) const
108 // Make sure that Index is valid
110 return &table
[Index
];
113 int TLB::probeEntry(Addr vpn
,uint8_t asn
) const
115 // assume not found...
116 MipsISA::PTE
*retval
= NULL
;
118 PageTable::const_iterator i
= lookupTable
.find(vpn
);
119 if (i
!= lookupTable
.end()) {
120 while (i
->first
== vpn
) {
121 int index
= i
->second
;
122 MipsISA::PTE
*pte
= &table
[index
];
124 /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
125 Addr Mask
= pte
->Mask
;
126 Addr InvMask
= ~Mask
;
128 if(((vpn
& InvMask
) == (VPN
& InvMask
)) && (pte
->G
|| (asn
== pte
->asid
)))
129 { // We have a VPN + ASID Match
138 DPRINTF(MipsPRA
,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn
,asn
,Ind
);
142 TLB::checkCacheability(RequestPtr
&req
)
144 Addr VAddrUncacheable
= 0xA0000000;
145 // In MIPS, cacheability is controlled by certain bits of the virtual address
146 // or by the TLB entry
147 if((req
->getVaddr() & VAddrUncacheable
) == VAddrUncacheable
) {
148 // mark request as uncacheable
149 req
->setFlags(Request::UNCACHEABLE
);
153 void TLB::insertAt(MipsISA::PTE
&pte
, unsigned Index
, int _smallPages
)
155 smallPages
=_smallPages
;
157 warn("Attempted to write at index (%d) beyond TLB size (%d)",Index
,size
);
160 DPRINTF(TLB
,"TLB[%d]: %x %x %x %x\n",Index
,pte
.Mask
<<11,((pte
.VPN
<< 11) | pte
.asid
),((pte
.PFN0
<<6) | (pte
.C0
<< 3) | (pte
.D0
<< 2) | (pte
.V0
<<1) | pte
.G
),
161 ((pte
.PFN1
<<6) | (pte
.C1
<< 3) | (pte
.D1
<< 2) | (pte
.V1
<<1) | pte
.G
));
162 if(table
[Index
].V0
== true || table
[Index
].V1
== true){ // Previous entry is valid
163 PageTable::iterator i
= lookupTable
.find(table
[Index
].VPN
);
164 lookupTable
.erase(i
);
167 // Update fast lookup table
168 lookupTable
.insert(make_pair(table
[Index
].VPN
, Index
));
169 // int TestIndex=probeEntry(pte.VPN,pte.asid);
170 // warn("Inserted at: %d, Found at: %d (%x)\n",Index,TestIndex,pte.Mask);
175 // insert a new TLB entry
177 TLB::insert(Addr addr
, MipsISA::PTE
&pte
)
179 fatal("TLB Insert not yet implemented\n");
182 /* MipsISA::VAddr vaddr = addr;
183 if (table[nlu].valid) {
184 Addr oldvpn = table[nlu].tag;
185 PageTable::iterator i = lookupTable.find(oldvpn);
187 if (i == lookupTable.end())
188 panic("TLB entry not found in lookupTable");
191 while ((index = i->second) != nlu) {
192 if (table[index].tag != oldvpn)
193 panic("TLB entry not found in lookupTable");
198 DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn);
200 lookupTable.erase(i);
203 DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn);
206 table[nlu].tag = vaddr.vpn();
207 table[nlu].valid = true;
209 lookupTable.insert(make_pair(vaddr.vpn(), nlu));
217 DPRINTF(TLB
, "flushAll\n");
218 memset(table
, 0, sizeof(MipsISA::PTE
[size
]));
224 TLB::serialize(ostream
&os
)
226 SERIALIZE_SCALAR(size
);
227 SERIALIZE_SCALAR(nlu
);
229 for (int i
= 0; i
< size
; i
++) {
230 nameOut(os
, csprintf("%s.PTE%d", name(), i
));
231 table
[i
].serialize(os
);
236 TLB::unserialize(Checkpoint
*cp
, const string
§ion
)
238 UNSERIALIZE_SCALAR(size
);
239 UNSERIALIZE_SCALAR(nlu
);
241 for (int i
= 0; i
< size
; i
++) {
242 table
[i
].unserialize(cp
, csprintf("%s.PTE%d", section
, i
));
243 if (table
[i
].V0
|| table
[i
].V1
) {
244 lookupTable
.insert(make_pair(table
[i
].VPN
, i
));
253 .name(name() + ".read_hits")
254 .desc("DTB read hits")
258 .name(name() + ".read_misses")
259 .desc("DTB read misses")
264 .name(name() + ".read_accesses")
265 .desc("DTB read accesses")
269 .name(name() + ".write_hits")
270 .desc("DTB write hits")
274 .name(name() + ".write_misses")
275 .desc("DTB write misses")
280 .name(name() + ".write_accesses")
281 .desc("DTB write accesses")
285 .name(name() + ".hits")
290 .name(name() + ".misses")
295 .name(name() + ".invalids")
296 .desc("DTB access violations")
300 .name(name() + ".accesses")
301 .desc("DTB accesses")
304 hits
= read_hits
+ write_hits
;
305 misses
= read_misses
+ write_misses
;
306 accesses
= read_accesses
+ write_accesses
;
310 TLB::translateInst(RequestPtr req
, ThreadContext
*tc
)
313 Process
* p
= tc
->getProcessPtr();
315 Fault fault
= p
->pTable
->translate(req
);
321 if(MipsISA::IsKSeg0(req
->getVaddr()))
323 // Address will not be translated through TLB, set response, and go!
324 req
->setPaddr(MipsISA::KSeg02Phys(req
->getVaddr()));
325 if(MipsISA::getOperatingMode(tc
->readMiscReg(MipsISA::Status
)) != mode_kernel
|| req
->isMisaligned())
327 AddressErrorFault
*Flt
= new AddressErrorFault();
328 /* BadVAddr must be set */
329 Flt
->BadVAddr
= req
->getVaddr();
333 else if(MipsISA::IsKSeg1(req
->getVaddr()))
335 // Address will not be translated through TLB, set response, and go!
336 req
->setPaddr(MipsISA::KSeg02Phys(req
->getVaddr()));
340 /* This is an optimization - smallPages is updated every time a TLB operation is performed
341 That way, we don't need to look at Config3 _ SP and PageGrain _ ESP every time we
345 VPN
=((req
->getVaddr() >> 11));
347 VPN
=((req
->getVaddr() >> 11) & 0xFFFFFFFC);
349 uint8_t Asid
= req
->getAsid();
350 if(req
->isMisaligned()){ // Unaligned address!
351 AddressErrorFault
*Flt
= new AddressErrorFault();
352 /* BadVAddr must be set */
353 Flt
->BadVAddr
= req
->getVaddr();
356 MipsISA::PTE
*pte
= lookup(VPN
,Asid
);
358 {// Ok, found something
359 /* Check for valid bits */
362 if((((req
->getVaddr()) >> pte
->AddrShiftAmount
) & 1) ==0){
374 ItbInvalidFault
*Flt
= new ItbInvalidFault();
375 /* EntryHi VPN, ASID fields must be set */
376 Flt
->EntryHi_Asid
= Asid
;
377 Flt
->EntryHi_VPN2
= (VPN
>>2);
378 Flt
->EntryHi_VPN2X
= (VPN
& 0x3);
380 /* BadVAddr must be set */
381 Flt
->BadVAddr
= req
->getVaddr();
383 /* Context must be set */
384 Flt
->Context_BadVPN2
= (VPN
>> 2);
388 {// Ok, this is really a match, set paddr
396 PAddr
>>= (pte
->AddrShiftAmount
-12);
397 PAddr
<<= pte
->AddrShiftAmount
;
398 PAddr
|= ((req
->getVaddr()) & pte
->OffsetMask
);
399 req
->setPaddr(PAddr
);
405 { // Didn't find any match, return a TLB Refill Exception
407 ItbRefillFault
*Flt
=new ItbRefillFault();
408 /* EntryHi VPN, ASID fields must be set */
409 Flt
->EntryHi_Asid
= Asid
;
410 Flt
->EntryHi_VPN2
= (VPN
>>2);
411 Flt
->EntryHi_VPN2X
= (VPN
& 0x3);
414 /* BadVAddr must be set */
415 Flt
->BadVAddr
= req
->getVaddr();
417 /* Context must be set */
418 Flt
->Context_BadVPN2
= (VPN
>> 2);
422 return checkCacheability(req
);
427 TLB::translateData(RequestPtr req
, ThreadContext
*tc
, bool write
)
430 //@TODO: This should actually use TLB instead of going directly
431 // to the page table in syscall mode.
433 * Check for alignment faults
435 if (req
->getVaddr() & (req
->getSize() - 1)) {
436 DPRINTF(TLB
, "Alignment Fault on %#x, size = %d", req
->getVaddr(),
438 return new AlignmentFault();
442 Process
* p
= tc
->getProcessPtr();
444 Fault fault
= p
->pTable
->translate(req
);
450 if(MipsISA::IsKSeg0(req
->getVaddr()))
452 // Address will not be translated through TLB, set response, and go!
453 req
->setPaddr(MipsISA::KSeg02Phys(req
->getVaddr()));
454 if(MipsISA::getOperatingMode(tc
->readMiscReg(MipsISA::Status
)) != mode_kernel
|| req
->isMisaligned())
456 StoreAddressErrorFault
*Flt
= new StoreAddressErrorFault();
457 /* BadVAddr must be set */
458 Flt
->BadVAddr
= req
->getVaddr();
463 else if(MipsISA::IsKSeg1(req
->getVaddr()))
465 // Address will not be translated through TLB, set response, and go!
466 req
->setPaddr(MipsISA::KSeg02Phys(req
->getVaddr()));
470 /* This is an optimization - smallPages is updated every time a TLB operation is performed
471 That way, we don't need to look at Config3 _ SP and PageGrain _ ESP every time we
473 Addr VPN
=((req
->getVaddr() >> 11) & 0xFFFFFFFC);
475 VPN
=((req
->getVaddr() >> 11));
477 uint8_t Asid
= req
->getAsid();
478 MipsISA::PTE
*pte
= lookup(VPN
,Asid
);
479 if(req
->isMisaligned()){ // Unaligned address!
480 StoreAddressErrorFault
*Flt
= new StoreAddressErrorFault();
481 /* BadVAddr must be set */
482 Flt
->BadVAddr
= req
->getVaddr();
486 {// Ok, found something
487 /* Check for valid bits */
491 if(((((req
->getVaddr()) >> pte
->AddrShiftAmount
) & 1)) ==0){
507 DtbInvalidFault
*Flt
= new DtbInvalidFault();
508 /* EntryHi VPN, ASID fields must be set */
509 Flt
->EntryHi_Asid
= Asid
;
510 Flt
->EntryHi_VPN2
= (VPN
>>2);
511 Flt
->EntryHi_VPN2X
= (VPN
& 0x3);
514 /* BadVAddr must be set */
515 Flt
->BadVAddr
= req
->getVaddr();
517 /* Context must be set */
518 Flt
->Context_BadVPN2
= (VPN
>> 2);
523 {// Ok, this is really a match, set paddr
527 TLBModifiedFault
*Flt
= new TLBModifiedFault();
528 /* EntryHi VPN, ASID fields must be set */
529 Flt
->EntryHi_Asid
= Asid
;
530 Flt
->EntryHi_VPN2
= (VPN
>>2);
531 Flt
->EntryHi_VPN2X
= (VPN
& 0x3);
534 /* BadVAddr must be set */
535 Flt
->BadVAddr
= req
->getVaddr();
537 /* Context must be set */
538 Flt
->Context_BadVPN2
= (VPN
>> 2);
548 PAddr
>>= (pte
->AddrShiftAmount
-12);
549 PAddr
<<= pte
->AddrShiftAmount
;
550 PAddr
|= ((req
->getVaddr()) & pte
->OffsetMask
);
551 req
->setPaddr(PAddr
);
555 { // Didn't find any match, return a TLB Refill Exception
557 DtbRefillFault
*Flt
=new DtbRefillFault();
558 /* EntryHi VPN, ASID fields must be set */
559 Flt
->EntryHi_Asid
= Asid
;
560 Flt
->EntryHi_VPN2
= (VPN
>>2);
561 Flt
->EntryHi_VPN2X
= (VPN
& 0x3);
564 /* BadVAddr must be set */
565 Flt
->BadVAddr
= req
->getVaddr();
567 /* Context must be set */
568 Flt
->Context_BadVPN2
= (VPN
>> 2);
572 return checkCacheability(req
);
577 TLB::translateAtomic(RequestPtr req
, ThreadContext
*tc
, Mode mode
)
580 return translateInst(req
, tc
);
582 return translateData(req
, tc
, mode
== Write
);
586 TLB::translateTiming(RequestPtr req
, ThreadContext
*tc
,
587 Translation
*translation
, Mode mode
)
590 translation
->finish(translateAtomic(req
, tc
, mode
), req
, tc
, mode
);
595 TLB::index(bool advance
)
597 MipsISA::PTE
*pte
= &table
[nlu
];
606 MipsTLBParams::create()
608 return new MipsISA::TLB(this);