src/arch/mips/tlb.cc

   1 /*
   2  * Copyright (c) 2001-2005 The Regents of The University of Michigan
   3  * Copyright (c) 2007 MIPS Technologies, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * Authors: Nathan Binkert
  30  *          Steve Reinhardt
  31  *          Jaidev Patwardhan
  32  */
  33
  34 #include <string>
  35 #include <vector>
  36
  37 #include "arch/mips/faults.hh"
  38 #include "arch/mips/pagetable.hh"
  39 #include "arch/mips/pra_constants.hh"
  40 #include "arch/mips/tlb.hh"
  41 #include "arch/mips/utility.hh"
  42 #include "base/inifile.hh"
  43 #include "base/str.hh"
  44 #include "base/trace.hh"
  45 #include "cpu/thread_context.hh"
  46 #include "debug/MipsPRA.hh"
  47 #include "debug/TLB.hh"
  48 #include "mem/page_table.hh"
  49 #include "params/MipsTLB.hh"
  50 #include "sim/process.hh"
  51
  52 using namespace std;
  53 using namespace MipsISA;
  54
  55 ///////////////////////////////////////////////////////////////////////
  56 //
  57 //  MIPS TLB
  58 //
  59
  60 static inline mode_type
  61 getOperatingMode(MiscReg Stat)
  62 {
  63     if ((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0) {
  64         return mode_kernel;
  65     } else if ((Stat & 0x18) == 0x8) {
  66         return mode_supervisor;
  67     } else if ((Stat & 0x18) == 0x10) {
  68         return mode_user;
  69     } else {
  70         return mode_number;
  71     }
  72 }
  73
  74
  75 TLB::TLB(const Params *p)
  76     : BaseTLB(p), size(p->size), nlu(0)
  77 {
  78     table = new PTE[size];
  79     memset(table, 0, sizeof(PTE[size]));
  80     smallPages = 0;
  81 }
  82
  83 TLB::~TLB()
  84 {
  85     if (table)
  86         delete [] table;
  87 }
  88
  89 // look up an entry in the TLB
  90 MipsISA::PTE *
  91 TLB::lookup(Addr vpn, uint8_t asn) const
  92 {
  93     // assume not found...
  94     PTE *retval = NULL;
  95     PageTable::const_iterator i = lookupTable.find(vpn);
  96     if (i != lookupTable.end()) {
  97         while (i->first == vpn) {
  98             int index = i->second;
  99             PTE *pte = &table[index];
 100
 101             /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
 102             Addr Mask = pte->Mask;
 103             Addr InvMask = ~Mask;
 104             Addr VPN  = pte->VPN;
 105             if (((vpn & InvMask) == (VPN & InvMask)) &&
 106                     (pte->G  || (asn == pte->asid))) {
 107                 // We have a VPN + ASID Match
 108                 retval = pte;
 109                 break;
 110             }
 111             ++i;
 112         }
 113     }
 114
 115     DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
 116             retval ? "hit" : "miss", retval ? retval->PFN1 : 0);
 117     return retval;
 118 }
 119
 120 MipsISA::PTE*
 121 TLB::getEntry(unsigned Index) const
 122 {
 123     // Make sure that Index is valid
 124     assert(Index<size);
 125     return &table[Index];
 126 }
 127
 128 int
 129 TLB::probeEntry(Addr vpn, uint8_t asn) const
 130 {
 131     // assume not found...
 132     int Ind = -1;
 133     PageTable::const_iterator i = lookupTable.find(vpn);
 134     if (i != lookupTable.end()) {
 135         while (i->first == vpn) {
 136             int index = i->second;
 137             PTE *pte = &table[index];
 138
 139             /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
 140             Addr Mask = pte->Mask;
 141             Addr InvMask = ~Mask;
 142             Addr VPN = pte->VPN;
 143             if (((vpn & InvMask) == (VPN & InvMask)) &&
 144                     (pte->G  || (asn == pte->asid))) {
 145                 // We have a VPN + ASID Match
 146                 Ind = index;
 147                 break;
 148             }
 149             ++i;
 150         }
 151     }
 152     DPRINTF(MipsPRA,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn,asn,Ind);
 153     return Ind;
 154 }
 155
 156 inline Fault
 157 TLB::checkCacheability(RequestPtr &req)
 158 {
 159     Addr VAddrUncacheable = 0xA0000000;
 160     // In MIPS, cacheability is controlled by certain bits of the virtual
 161     // address or by the TLB entry
 162     if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
 163         // mark request as uncacheable
 164         req->setFlags(Request::UNCACHEABLE);
 165     }
 166     return NoFault;
 167 }
 168
 169 void
 170 TLB::insertAt(PTE &pte, unsigned Index, int _smallPages)
 171 {
 172     smallPages = _smallPages;
 173     if (Index > size) {
 174         warn("Attempted to write at index (%d) beyond TLB size (%d)",
 175                 Index, size);
 176     } else {
 177         // Update TLB
 178         DPRINTF(TLB, "TLB[%d]: %x %x %x %x\n",
 179                 Index, pte.Mask << 11,
 180                 ((pte.VPN << 11) | pte.asid),
 181                 ((pte.PFN0 << 6) | (pte.C0 << 3) |
 182                  (pte.D0 << 2) | (pte.V0 <<1) | pte.G),
 183                 ((pte.PFN1 <<6) | (pte.C1 << 3) |
 184                  (pte.D1 << 2) | (pte.V1 <<1) | pte.G));
 185         if (table[Index].V0 == true || table[Index].V1 == true) {
 186             // Previous entry is valid
 187             PageTable::iterator i = lookupTable.find(table[Index].VPN);
 188             lookupTable.erase(i);
 189         }
 190         table[Index]=pte;
 191         // Update fast lookup table
 192         lookupTable.insert(make_pair(table[Index].VPN, Index));
 193     }
 194 }
 195
 196 // insert a new TLB entry
 197 void
 198 TLB::insert(Addr addr, PTE &pte)
 199 {
 200     fatal("TLB Insert not yet implemented\n");
 201 }
 202
 203 void
 204 TLB::flushAll()
 205 {
 206     DPRINTF(TLB, "flushAll\n");
 207     memset(table, 0, sizeof(PTE[size]));
 208     lookupTable.clear();
 209     nlu = 0;
 210 }
 211
 212 void
 213 TLB::serialize(ostream &os)
 214 {
 215     SERIALIZE_SCALAR(size);
 216     SERIALIZE_SCALAR(nlu);
 217
 218     for (int i = 0; i < size; i++) {
 219         nameOut(os, csprintf("%s.PTE%d", name(), i));
 220         table[i].serialize(os);
 221     }
 222 }
 223
 224 void
 225 TLB::unserialize(Checkpoint *cp, const string &section)
 226 {
 227     UNSERIALIZE_SCALAR(size);
 228     UNSERIALIZE_SCALAR(nlu);
 229
 230     for (int i = 0; i < size; i++) {
 231         table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
 232         if (table[i].V0 || table[i].V1) {
 233             lookupTable.insert(make_pair(table[i].VPN, i));
 234         }
 235     }
 236 }
 237
 238 void
 239 TLB::regStats()
 240 {
 241     read_hits
 242         .name(name() + ".read_hits")
 243         .desc("DTB read hits")
 244         ;
 245
 246     read_misses
 247         .name(name() + ".read_misses")
 248         .desc("DTB read misses")
 249         ;
 250
 251
 252     read_accesses
 253         .name(name() + ".read_accesses")
 254         .desc("DTB read accesses")
 255         ;
 256
 257     write_hits
 258         .name(name() + ".write_hits")
 259         .desc("DTB write hits")
 260         ;
 261
 262     write_misses
 263         .name(name() + ".write_misses")
 264         .desc("DTB write misses")
 265         ;
 266
 267
 268     write_accesses
 269         .name(name() + ".write_accesses")
 270         .desc("DTB write accesses")
 271         ;
 272
 273     hits
 274         .name(name() + ".hits")
 275         .desc("DTB hits")
 276         ;
 277
 278     misses
 279         .name(name() + ".misses")
 280         .desc("DTB misses")
 281         ;
 282
 283     accesses
 284         .name(name() + ".accesses")
 285         .desc("DTB accesses")
 286         ;
 287
 288     hits = read_hits + write_hits;
 289     misses = read_misses + write_misses;
 290     accesses = read_accesses + write_accesses;
 291 }
 292
 293 Fault
 294 TLB::translateInst(RequestPtr req, ThreadContext *tc)
 295 {
 296     if (!FullSystem) {
 297         Process * p = tc->getProcessPtr();
 298
 299         Fault fault = p->pTable->translate(req);
 300         if (fault != NoFault)
 301             return fault;
 302
 303         return NoFault;
 304     } else {
 305         panic("translateInst not implemented in MIPS.\n");
 306     }
 307 }
 308
 309 Fault
 310 TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
 311 {
 312     if (!FullSystem) {
 313         //@TODO: This should actually use TLB instead of going directly
 314         //       to the page table in syscall mode.
 315         /**
 316          * Check for alignment faults
 317          */
 318         if (req->getVaddr() & (req->getSize() - 1)) {
 319             DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
 320                     req->getSize());
 321             return new AddressErrorFault(req->getVaddr(), write);
 322         }
 323
 324
 325         Process * p = tc->getProcessPtr();
 326
 327         Fault fault = p->pTable->translate(req);
 328         if (fault != NoFault)
 329             return fault;
 330
 331         return NoFault;
 332     } else {
 333         panic("translateData not implemented in MIPS.\n");
 334     }
 335 }
 336
 337 Fault
 338 TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
 339 {
 340     if (mode == Execute)
 341         return translateInst(req, tc);
 342     else
 343         return translateData(req, tc, mode == Write);
 344 }
 345
 346 void
 347 TLB::translateTiming(RequestPtr req, ThreadContext *tc,
 348         Translation *translation, Mode mode)
 349 {
 350     assert(translation);
 351     translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
 352 }
 353
 354
 355 MipsISA::PTE &
 356 TLB::index(bool advance)
 357 {
 358     PTE *pte = &table[nlu];
 359
 360     if (advance)
 361         nextnlu();
 362
 363     return *pte;
 364 }
 365
 366 MipsISA::TLB *
 367 MipsTLBParams::create()
 368 {
 369     return new TLB(this);
 370 }