2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * Authors: Nathan Binkert
37 #include "arch/mips/faults.hh"
38 #include "arch/mips/pagetable.hh"
39 #include "arch/mips/pra_constants.hh"
40 #include "arch/mips/tlb.hh"
41 #include "arch/mips/utility.hh"
42 #include "base/inifile.hh"
43 #include "base/str.hh"
44 #include "base/trace.hh"
45 #include "cpu/thread_context.hh"
46 #include "debug/MipsPRA.hh"
47 #include "debug/TLB.hh"
48 #include "mem/page_table.hh"
49 #include "params/MipsTLB.hh"
50 #include "sim/process.hh"
53 using namespace MipsISA
;
55 ///////////////////////////////////////////////////////////////////////
60 static inline mode_type
61 getOperatingMode(MiscReg Stat
)
63 if ((Stat
& 0x10000006) != 0 || (Stat
& 0x18) ==0) {
65 } else if ((Stat
& 0x18) == 0x8) {
66 return mode_supervisor
;
67 } else if ((Stat
& 0x18) == 0x10) {
75 TLB::TLB(const Params
*p
)
76 : BaseTLB(p
), size(p
->size
), nlu(0)
78 table
= new PTE
[size
];
79 memset(table
, 0, sizeof(PTE
[size
]));
89 // look up an entry in the TLB
91 TLB::lookup(Addr vpn
, uint8_t asn
) const
93 // assume not found...
95 PageTable::const_iterator i
= lookupTable
.find(vpn
);
96 if (i
!= lookupTable
.end()) {
97 while (i
->first
== vpn
) {
98 int index
= i
->second
;
99 PTE
*pte
= &table
[index
];
101 /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
102 Addr Mask
= pte
->Mask
;
103 Addr InvMask
= ~Mask
;
105 if (((vpn
& InvMask
) == (VPN
& InvMask
)) &&
106 (pte
->G
|| (asn
== pte
->asid
))) {
107 // We have a VPN + ASID Match
115 DPRINTF(TLB
, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn
, (int)asn
,
116 retval
? "hit" : "miss", retval
? retval
->PFN1
: 0);
121 TLB::getEntry(unsigned Index
) const
123 // Make sure that Index is valid
125 return &table
[Index
];
129 TLB::probeEntry(Addr vpn
, uint8_t asn
) const
131 // assume not found...
134 PageTable::const_iterator i
= lookupTable
.find(vpn
);
135 if (i
!= lookupTable
.end()) {
136 while (i
->first
== vpn
) {
137 int index
= i
->second
;
138 PTE
*pte
= &table
[index
];
140 /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
141 Addr Mask
= pte
->Mask
;
142 Addr InvMask
= ~Mask
;
144 if (((vpn
& InvMask
) == (VPN
& InvMask
)) &&
145 (pte
->G
|| (asn
== pte
->asid
))) {
146 // We have a VPN + ASID Match
154 DPRINTF(MipsPRA
,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn
,asn
,Ind
);
159 TLB::checkCacheability(RequestPtr
&req
)
161 Addr VAddrUncacheable
= 0xA0000000;
162 // In MIPS, cacheability is controlled by certain bits of the virtual
163 // address or by the TLB entry
164 if ((req
->getVaddr() & VAddrUncacheable
) == VAddrUncacheable
) {
165 // mark request as uncacheable
166 req
->setFlags(Request::UNCACHEABLE
);
172 TLB::insertAt(PTE
&pte
, unsigned Index
, int _smallPages
)
174 smallPages
= _smallPages
;
176 warn("Attempted to write at index (%d) beyond TLB size (%d)",
180 DPRINTF(TLB
, "TLB[%d]: %x %x %x %x\n",
181 Index
, pte
.Mask
<< 11,
182 ((pte
.VPN
<< 11) | pte
.asid
),
183 ((pte
.PFN0
<< 6) | (pte
.C0
<< 3) |
184 (pte
.D0
<< 2) | (pte
.V0
<<1) | pte
.G
),
185 ((pte
.PFN1
<<6) | (pte
.C1
<< 3) |
186 (pte
.D1
<< 2) | (pte
.V1
<<1) | pte
.G
));
187 if (table
[Index
].V0
== true || table
[Index
].V1
== true) {
188 // Previous entry is valid
189 PageTable::iterator i
= lookupTable
.find(table
[Index
].VPN
);
190 lookupTable
.erase(i
);
193 // Update fast lookup table
194 lookupTable
.insert(make_pair(table
[Index
].VPN
, Index
));
198 // insert a new TLB entry
200 TLB::insert(Addr addr
, PTE
&pte
)
202 fatal("TLB Insert not yet implemented\n");
208 DPRINTF(TLB
, "flushAll\n");
209 memset(table
, 0, sizeof(PTE
[size
]));
215 TLB::serialize(ostream
&os
)
217 SERIALIZE_SCALAR(size
);
218 SERIALIZE_SCALAR(nlu
);
220 for (int i
= 0; i
< size
; i
++) {
221 nameOut(os
, csprintf("%s.PTE%d", name(), i
));
222 table
[i
].serialize(os
);
227 TLB::unserialize(Checkpoint
*cp
, const string
§ion
)
229 UNSERIALIZE_SCALAR(size
);
230 UNSERIALIZE_SCALAR(nlu
);
232 for (int i
= 0; i
< size
; i
++) {
233 table
[i
].unserialize(cp
, csprintf("%s.PTE%d", section
, i
));
234 if (table
[i
].V0
|| table
[i
].V1
) {
235 lookupTable
.insert(make_pair(table
[i
].VPN
, i
));
244 .name(name() + ".read_hits")
245 .desc("DTB read hits")
249 .name(name() + ".read_misses")
250 .desc("DTB read misses")
255 .name(name() + ".read_accesses")
256 .desc("DTB read accesses")
260 .name(name() + ".write_hits")
261 .desc("DTB write hits")
265 .name(name() + ".write_misses")
266 .desc("DTB write misses")
271 .name(name() + ".write_accesses")
272 .desc("DTB write accesses")
276 .name(name() + ".hits")
281 .name(name() + ".misses")
286 .name(name() + ".accesses")
287 .desc("DTB accesses")
290 hits
= read_hits
+ write_hits
;
291 misses
= read_misses
+ write_misses
;
292 accesses
= read_accesses
+ write_accesses
;
296 TLB::translateInst(RequestPtr req
, ThreadContext
*tc
)
299 Process
* p
= tc
->getProcessPtr();
301 Fault fault
= p
->pTable
->translate(req
);
302 if (fault
!= NoFault
)
307 panic("translateInst not implemented in MIPS.\n");
312 TLB::translateData(RequestPtr req
, ThreadContext
*tc
, bool write
)
315 //@TODO: This should actually use TLB instead of going directly
316 // to the page table in syscall mode.
318 * Check for alignment faults
320 if (req
->getVaddr() & (req
->getSize() - 1)) {
321 DPRINTF(TLB
, "Alignment Fault on %#x, size = %d", req
->getVaddr(),
323 return new AddressErrorFault(req
->getVaddr(), write
);
327 Process
* p
= tc
->getProcessPtr();
329 Fault fault
= p
->pTable
->translate(req
);
330 if (fault
!= NoFault
)
335 panic("translateData not implemented in MIPS.\n");
340 TLB::translateAtomic(RequestPtr req
, ThreadContext
*tc
, Mode mode
)
343 return translateInst(req
, tc
);
345 return translateData(req
, tc
, mode
== Write
);
349 TLB::translateTiming(RequestPtr req
, ThreadContext
*tc
,
350 Translation
*translation
, Mode mode
)
353 translation
->finish(translateAtomic(req
, tc
, mode
), req
, tc
, mode
);
358 TLB::index(bool advance
)
360 PTE
*pte
= &table
[nlu
];
369 MipsTLBParams::create()
371 return new TLB(this);