src/arch/mips/tlb.hh

   1 /*
   2  * Copyright (c) 2001-2005 The Regents of The University of Michigan
   3  * Copyright (c) 2007 MIPS Technologies, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * Authors: Nathan Binkert
  30  *          Steve Reinhardt
  31  *          Jaidev Patwardhan
  32  *          Korey Sewell
  33  */
  34
  35 #ifndef __ARCH_MIPS_TLB_HH__
  36 #define __ARCH_MIPS_TLB_HH__
  37
  38 #include <map>
  39
  40 #include "arch/mips/isa_traits.hh"
  41 #include "arch/mips/pagetable.hh"
  42 #include "arch/mips/utility.hh"
  43 #include "arch/mips/vtophys.hh"
  44 #include "base/statistics.hh"
  45 #include "mem/request.hh"
  46 #include "params/MipsTLB.hh"
  47 #include "sim/fault_fwd.hh"
  48 #include "sim/sim_object.hh"
  49 #include "sim/tlb.hh"
  50
  51 class ThreadContext;
  52
  53 /* MIPS does not distinguish between a DTLB and an ITLB -> unified TLB
  54    However, to maintain compatibility with other architectures, we'll
  55    simply create an ITLB and DTLB that will point to the real TLB */
  56 namespace MipsISA {
  57
  58 class TLB : public BaseTLB
  59 {
  60   protected:
  61     typedef std::multimap<Addr, int> PageTable;
  62     PageTable lookupTable;      // Quick lookup into page table
  63
  64     MipsISA::PTE *table;        // the Page Table
  65     int size;                   // TLB Size
  66     int nlu;                    // not last used entry (for replacement)
  67
  68     void nextnlu() { if (++nlu >= size) nlu = 0; }
  69     MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const;
  70
  71     mutable Stats::Scalar read_hits;
  72     mutable Stats::Scalar read_misses;
  73     mutable Stats::Scalar read_acv;
  74     mutable Stats::Scalar read_accesses;
  75     mutable Stats::Scalar write_hits;
  76     mutable Stats::Scalar write_misses;
  77     mutable Stats::Scalar write_acv;
  78     mutable Stats::Scalar write_accesses;
  79     Stats::Formula hits;
  80     Stats::Formula misses;
  81     Stats::Formula accesses;
  82
  83   public:
  84     typedef MipsTLBParams Params;
  85     TLB(const Params *p);
  86
  87     int probeEntry(Addr vpn,uint8_t) const;
  88     MipsISA::PTE *getEntry(unsigned) const;
  89     virtual ~TLB();
  90     int smallPages;
  91     int getsize() const { return size; }
  92
  93     MipsISA::PTE &index(bool advance = true);
  94     void insert(Addr vaddr, MipsISA::PTE &pte);
  95     void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages);
  96     void flushAll();
  97     void demapPage(Addr vaddr, uint64_t asn)
  98     {
  99         panic("demapPage unimplemented.\n");
 100     }
 101
 102     // static helper functions... really
 103     static bool validVirtualAddress(Addr vaddr);
 104
 105     static Fault checkCacheability(RequestPtr &req);
 106
 107     // Checkpointing
 108     void serialize(std::ostream &os);
 109     void unserialize(Checkpoint *cp, const std::string &section);
 110
 111     void regStats();
 112
 113     Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
 114     void translateTiming(RequestPtr req, ThreadContext *tc,
 115             Translation *translation, Mode mode);
 116
 117     /** Function stub for CheckerCPU compilation issues. MIPS does not
 118      *  support the Checker model at the moment.
 119      */
 120     Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
 121     Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
 122
 123   private:
 124     Fault translateInst(RequestPtr req, ThreadContext *tc);
 125     Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
 126 };
 127
 128 }
 129
 130
 131
 132 #endif // __MIPS_MEMORY_HH__