src/arch/mips/tlb.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Jaidev Patwardhan
  29  */
  30
  31 #ifndef __ARCH_MIPS_TLB_HH__
  32 #define __ARCH_MIPS_TLB_HH__
  33
  34 #include <map>
  35
  36 #include "arch/mips/isa_traits.hh"
  37 #include "arch/mips/utility.hh"
  38 #include "arch/mips/vtophys.hh"
  39 #include "arch/mips/pagetable.hh"
  40 #include "base/statistics.hh"
  41 #include "mem/request.hh"
  42 #include "params/MipsDTB.hh"
  43 #include "params/MipsITB.hh"
  44 #include "sim/faults.hh"
  45 #include "sim/tlb.hh"
  46 #include "sim/sim_object.hh"
  47
  48 class ThreadContext;
  49
  50 /* MIPS does not distinguish between a DTLB and an ITLB -> unified TLB
  51    However, to maintain compatibility with other architectures, we'll
  52    simply create an ITLB and DTLB that will point to the real TLB */
  53 namespace MipsISA {
  54
  55 // WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
  56 struct TlbEntry
  57 {
  58     Addr _pageStart;
  59     TlbEntry() {}
  60     TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
  61
  62     Addr pageStart()
  63     {
  64         return _pageStart;
  65     }
  66
  67     void serialize(std::ostream &os)
  68     {
  69         SERIALIZE_SCALAR(_pageStart);
  70     }
  71
  72     void unserialize(Checkpoint *cp, const std::string &section)
  73     {
  74         UNSERIALIZE_SCALAR(_pageStart);
  75     }
  76
  77 };
  78
  79 class TLB : public SimObject
  80 {
  81   protected:
  82     typedef std::multimap<Addr, int> PageTable;
  83     PageTable lookupTable;      // Quick lookup into page table
  84
  85     MipsISA::PTE *table;        // the Page Table
  86     int size;                   // TLB Size
  87     int nlu;                    // not last used entry (for replacement)
  88
  89     void nextnlu() { if (++nlu >= size) nlu = 0; }
  90     MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const;
  91
  92     mutable Stats::Scalar<> read_hits;
  93     mutable Stats::Scalar<> read_misses;
  94     mutable Stats::Scalar<> read_acv;
  95     mutable Stats::Scalar<> read_accesses;
  96     mutable Stats::Scalar<> write_hits;
  97     mutable Stats::Scalar<> write_misses;
  98     mutable Stats::Scalar<> write_acv;
  99     mutable Stats::Scalar<> write_accesses;
 100     Stats::Formula hits;
 101     Stats::Formula misses;
 102     Stats::Formula invalids;
 103     Stats::Formula accesses;
 104
 105   public:
 106     typedef MipsTLBParams Params;
 107     TLB(const Params *p);
 108
 109     int probeEntry(Addr vpn,uint8_t) const;
 110     MipsISA::PTE *getEntry(unsigned) const;
 111     virtual ~TLB();
 112     int smallPages;
 113     int getsize() const { return size; }
 114
 115     MipsISA::PTE &index(bool advance = true);
 116     void insert(Addr vaddr, MipsISA::PTE &pte);
 117     void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages);
 118     void flushAll();
 119
 120     // static helper functions... really
 121     static bool validVirtualAddress(Addr vaddr);
 122
 123     static Fault checkCacheability(RequestPtr &req);
 124
 125     // Checkpointing
 126     void serialize(std::ostream &os);
 127     void unserialize(Checkpoint *cp, const std::string &section);
 128
 129     void regStats();
 130 };
 131
 132 class ITB : public TLB {
 133   public:
 134     typedef MipsTLBParams Params;
 135     ITB(const Params *p);
 136
 137     Fault translate(RequestPtr &req, ThreadContext *tc);
 138 };
 139
 140 class DTB : public TLB {
 141   public:
 142     typedef MipsTLBParams Params;
 143     DTB(const Params *p);
 144
 145     Fault translate(RequestPtr &req, ThreadContext *tc, bool write = false);
 146 };
 147
 148 class UTB : public ITB, public DTB {
 149   public:
 150     typedef MipsTLBParams Params;
 151     UTB(const Params *p);
 152
 153 };
 154
 155 }
 156
 157
 158
 159 #endif // __MIPS_MEMORY_HH__