src/arch/mips/types.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  */
  30
  31 #ifndef __ARCH_MIPS_TYPES_HH__
  32 #define __ARCH_MIPS_TYPES_HH__
  33
  34 #include "arch/generic/types.hh"
  35 #include "base/types.hh"
  36
  37 namespace MipsISA
  38 {
  39
  40 typedef uint32_t MachInst;
  41 typedef uint64_t ExtMachInst;
  42
  43 typedef GenericISA::DelaySlotPCState<MachInst> PCState;
  44
  45 typedef uint64_t LargestRead;
  46
  47 //used in FP convert & round function
  48 enum ConvertType{
  49     SINGLE_TO_DOUBLE,
  50     SINGLE_TO_WORD,
  51     SINGLE_TO_LONG,
  52
  53     DOUBLE_TO_SINGLE,
  54     DOUBLE_TO_WORD,
  55     DOUBLE_TO_LONG,
  56
  57     LONG_TO_SINGLE,
  58     LONG_TO_DOUBLE,
  59     LONG_TO_WORD,
  60     LONG_TO_PS,
  61
  62     WORD_TO_SINGLE,
  63     WORD_TO_DOUBLE,
  64     WORD_TO_LONG,
  65     WORD_TO_PS,
  66
  67     PL_TO_SINGLE,
  68     PU_TO_SINGLE
  69 };
  70
  71 //used in FP convert & round function
  72 enum RoundMode{
  73     RND_ZERO,
  74     RND_DOWN,
  75     RND_UP,
  76     RND_NEAREST
  77 };
  78
  79 struct CoreSpecific {
  80     CoreSpecific()
  81         : CP0_IntCtl_IPTI(0), CP0_IntCtl_IPPCI(0), CP0_SrsCtl_HSS(0),
  82           CP0_PRId_CompanyOptions(0), CP0_PRId_CompanyID(0),
  83           CP0_PRId_ProcessorID(0), CP0_PRId_Revision(0),
  84           CP0_EBase_CPUNum(0), CP0_Config_BE(0), CP0_Config_AT(0),
  85           CP0_Config_AR(0), CP0_Config_MT(0), CP0_Config_VI(0),
  86           CP0_Config1_M(0), CP0_Config1_MMU(0), CP0_Config1_IS(0),
  87           CP0_Config1_IL(0), CP0_Config1_IA(0), CP0_Config1_DS(0),
  88           CP0_Config1_DL(0), CP0_Config1_DA(0), CP0_Config1_C2(false),
  89           CP0_Config1_MD(false), CP0_Config1_PC(false), CP0_Config1_WR(false),
  90           CP0_Config1_CA(false), CP0_Config1_EP(false), CP0_Config1_FP(false),
  91           CP0_Config2_M(false), CP0_Config2_TU(0), CP0_Config2_TS(0),
  92           CP0_Config2_TL(0), CP0_Config2_TA(0), CP0_Config2_SU(0),
  93           CP0_Config2_SS(0), CP0_Config2_SL(0), CP0_Config2_SA(0),
  94           CP0_Config3_M(false), CP0_Config3_DSPP(false), CP0_Config3_LPA(false),
  95           CP0_Config3_VEIC(false), CP0_Config3_VInt(false),
  96           CP0_Config3_SP(false), CP0_Config3_MT(false), CP0_Config3_SM(false),
  97           CP0_Config3_TL(false), CP0_WatchHi_M(false), CP0_PerfCtr_M(false),
  98           CP0_PerfCtr_W(false), CP0_PRId(0), CP0_Config(0), CP0_Config1(0),
  99           CP0_Config2(0), CP0_Config3(0)
 100     { }
 101
 102       // MIPS CP0 State - First individual variables
 103       // Page numbers refer to revision 2.50 (July 2005) of the MIPS32 ARM,
 104       // Volume III (PRA)
 105       unsigned CP0_IntCtl_IPTI; // Page 93, IP Timer Interrupt
 106       unsigned CP0_IntCtl_IPPCI; // Page 94, IP Performance Counter Interrupt
 107       unsigned CP0_SrsCtl_HSS; // Page 95, Highest Implemented Shadow Set
 108       unsigned CP0_PRId_CompanyOptions; // Page 105, Manufacture options
 109       unsigned CP0_PRId_CompanyID; // Page 105, Company ID - (0-255, 1=>MIPS)
 110       unsigned CP0_PRId_ProcessorID; // Page 105
 111       unsigned CP0_PRId_Revision; // Page 105
 112       unsigned CP0_EBase_CPUNum; // Page 106, CPU Number in a multiprocessor
 113                                  //system
 114       unsigned CP0_Config_BE; // Page 108, Big/Little Endian mode
 115       unsigned CP0_Config_AT; //Page 109
 116       unsigned CP0_Config_AR; //Page 109
 117       unsigned CP0_Config_MT; //Page 109
 118       unsigned CP0_Config_VI; //Page 109
 119       unsigned CP0_Config1_M; // Page 110
 120       unsigned CP0_Config1_MMU; // Page 110
 121       unsigned CP0_Config1_IS; // Page 110
 122       unsigned CP0_Config1_IL; // Page 111
 123       unsigned CP0_Config1_IA; // Page 111
 124       unsigned CP0_Config1_DS; // Page 111
 125       unsigned CP0_Config1_DL; // Page 112
 126       unsigned CP0_Config1_DA; // Page 112
 127       bool CP0_Config1_C2; // Page 112
 128       bool CP0_Config1_MD;// Page 112 - Technically not used in MIPS32
 129       bool CP0_Config1_PC;// Page 112
 130       bool CP0_Config1_WR;// Page 113
 131       bool CP0_Config1_CA;// Page 113
 132       bool CP0_Config1_EP;// Page 113
 133       bool CP0_Config1_FP;// Page 113
 134       bool CP0_Config2_M; // Page 114
 135       unsigned CP0_Config2_TU;// Page 114
 136       unsigned CP0_Config2_TS;// Page 114
 137       unsigned CP0_Config2_TL;// Page 115
 138       unsigned CP0_Config2_TA;// Page 115
 139       unsigned CP0_Config2_SU;// Page 115
 140       unsigned CP0_Config2_SS;// Page 115
 141       unsigned CP0_Config2_SL;// Page 116
 142       unsigned CP0_Config2_SA;// Page 116
 143       bool CP0_Config3_M; //// Page 117
 144       bool CP0_Config3_DSPP;// Page 117
 145       bool CP0_Config3_LPA;// Page 117
 146       bool CP0_Config3_VEIC;// Page 118
 147       bool CP0_Config3_VInt; // Page 118
 148       bool CP0_Config3_SP;// Page 118
 149       bool CP0_Config3_MT;// Page 119
 150       bool CP0_Config3_SM;// Page 119
 151       bool CP0_Config3_TL;// Page 119
 152
 153       bool CP0_WatchHi_M; // Page 124
 154       bool CP0_PerfCtr_M; // Page 130
 155       bool CP0_PerfCtr_W; // Page 130
 156
 157
 158       // Then, whole registers
 159       unsigned CP0_PRId;
 160       unsigned CP0_Config;
 161       unsigned CP0_Config1;
 162       unsigned CP0_Config2;
 163       unsigned CP0_Config3;
 164 };
 165
 166 } // namespace MipsISA
 167 #endif