2 * Copyright (c) 2007 MIPS Technologies, Inc.
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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28 * Authors: Korey Sewell
31 #ifndef __ARCH_MIPS_TYPES_HH__
32 #define __ARCH_MIPS_TYPES_HH__
34 #include "arch/generic/types.hh"
35 #include "base/types.hh"
40 typedef uint32_t MachInst;
41 typedef uint64_t ExtMachInst;
43 typedef GenericISA::DelaySlotPCState<MachInst> PCState;
45 typedef uint64_t LargestRead;
47 //used in FP convert & round function
71 //used in FP convert & round function
80 /* Note: It looks like it will be better to allow simulator users
81 to specify the values of individual variables instead of requiring
82 users to define the values of entire registers
83 Especially since a lot of these variables can be created from other
84 user parameters (cache descriptions)
87 // MIPS CP0 State - First individual variables
88 // Page numbers refer to revision 2.50 (July 2005) of the MIPS32 ARM,
90 unsigned CP0_IntCtl_IPTI; // Page 93, IP Timer Interrupt
91 unsigned CP0_IntCtl_IPPCI; // Page 94, IP Performance Counter Interrupt
92 unsigned CP0_SrsCtl_HSS; // Page 95, Highest Implemented Shadow Set
93 unsigned CP0_PRId_CompanyOptions; // Page 105, Manufacture options
94 unsigned CP0_PRId_CompanyID; // Page 105, Company ID - (0-255, 1=>MIPS)
95 unsigned CP0_PRId_ProcessorID; // Page 105
96 unsigned CP0_PRId_Revision; // Page 105
97 unsigned CP0_EBase_CPUNum; // Page 106, CPU Number in a multiprocessor
99 unsigned CP0_Config_BE; // Page 108, Big/Little Endian mode
100 unsigned CP0_Config_AT; //Page 109
101 unsigned CP0_Config_AR; //Page 109
102 unsigned CP0_Config_MT; //Page 109
103 unsigned CP0_Config_VI; //Page 109
104 unsigned CP0_Config1_M; // Page 110
105 unsigned CP0_Config1_MMU; // Page 110
106 unsigned CP0_Config1_IS; // Page 110
107 unsigned CP0_Config1_IL; // Page 111
108 unsigned CP0_Config1_IA; // Page 111
109 unsigned CP0_Config1_DS; // Page 111
110 unsigned CP0_Config1_DL; // Page 112
111 unsigned CP0_Config1_DA; // Page 112
112 bool CP0_Config1_C2; // Page 112
113 bool CP0_Config1_MD;// Page 112 - Technically not used in MIPS32
114 bool CP0_Config1_PC;// Page 112
115 bool CP0_Config1_WR;// Page 113
116 bool CP0_Config1_CA;// Page 113
117 bool CP0_Config1_EP;// Page 113
118 bool CP0_Config1_FP;// Page 113
119 bool CP0_Config2_M; // Page 114
120 unsigned CP0_Config2_TU;// Page 114
121 unsigned CP0_Config2_TS;// Page 114
122 unsigned CP0_Config2_TL;// Page 115
123 unsigned CP0_Config2_TA;// Page 115
124 unsigned CP0_Config2_SU;// Page 115
125 unsigned CP0_Config2_SS;// Page 115
126 unsigned CP0_Config2_SL;// Page 116
127 unsigned CP0_Config2_SA;// Page 116
128 bool CP0_Config3_M; //// Page 117
129 bool CP0_Config3_DSPP;// Page 117
130 bool CP0_Config3_LPA;// Page 117
131 bool CP0_Config3_VEIC;// Page 118
132 bool CP0_Config3_VInt; // Page 118
133 bool CP0_Config3_SP;// Page 118
134 bool CP0_Config3_MT;// Page 119
135 bool CP0_Config3_SM;// Page 119
136 bool CP0_Config3_TL;// Page 119
138 bool CP0_WatchHi_M; // Page 124
139 bool CP0_PerfCtr_M; // Page 130
140 bool CP0_PerfCtr_W; // Page 130
143 // Then, whole registers
146 unsigned CP0_Config1;
147 unsigned CP0_Config2;
148 unsigned CP0_Config3;
151 } // namespace MipsISA