src/arch/mips/utility.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  */
  30
  31 #include <cmath>
  32
  33 #include "arch/mips/isa_traits.hh"
  34 #include "arch/mips/registers.hh"
  35 #include "arch/mips/utility.hh"
  36 #include "arch/mips/vtophys.hh"
  37 #include "base/bitfield.hh"
  38 #include "base/misc.hh"
  39 #include "cpu/static_inst.hh"
  40 #include "cpu/thread_context.hh"
  41 #include "mem/fs_translating_port_proxy.hh"
  42 #include "sim/serialize.hh"
  43
  44
  45 using namespace MipsISA;
  46 using namespace std;
  47
  48 namespace MipsISA {
  49
  50 uint64_t
  51 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
  52 {
  53     panic("getArgument() not implemented\n");
  54     M5_DUMMY_RETURN
  55 }
  56
  57 uint64_t
  58 fpConvert(ConvertType cvt_type, double fp_val)
  59 {
  60
  61     switch (cvt_type)
  62     {
  63       case SINGLE_TO_DOUBLE:
  64         {
  65             double sdouble_val = fp_val;
  66             void  *sdouble_ptr = &sdouble_val;
  67             uint64_t sdp_bits  = *(uint64_t *) sdouble_ptr;
  68             return sdp_bits;
  69         }
  70
  71       case SINGLE_TO_WORD:
  72         {
  73             int32_t sword_val  = (int32_t) fp_val;
  74             void  *sword_ptr   = &sword_val;
  75             uint64_t sword_bits= *(uint32_t *) sword_ptr;
  76             return sword_bits;
  77         }
  78
  79       case WORD_TO_SINGLE:
  80         {
  81             float wfloat_val   = fp_val;
  82             void  *wfloat_ptr  = &wfloat_val;
  83             uint64_t wfloat_bits = *(uint32_t *) wfloat_ptr;
  84             return wfloat_bits;
  85         }
  86
  87       case WORD_TO_DOUBLE:
  88         {
  89             double wdouble_val = fp_val;
  90             void  *wdouble_ptr = &wdouble_val;
  91             uint64_t wdp_bits  = *(uint64_t *) wdouble_ptr;
  92             return wdp_bits;
  93         }
  94
  95       default:
  96         panic("Invalid Floating Point Conversion Type (%d). See \"types.hh\" for List of Conversions\n",cvt_type);
  97         return 0;
  98     }
  99 }
 100
 101 double
 102 roundFP(double val, int digits)
 103 {
 104     double digit_offset = pow(10.0,digits);
 105     val = val * digit_offset;
 106     val = val + 0.5;
 107     val = floor(val);
 108     val = val / digit_offset;
 109     return val;
 110 }
 111
 112 double
 113 truncFP(double val)
 114 {
 115     int trunc_val = (int) val;
 116     return (double) trunc_val;
 117 }
 118
 119 bool
 120 getCondCode(uint32_t fcsr, int cc_idx)
 121 {
 122     int shift = (cc_idx == 0) ? 23 : cc_idx + 24;
 123     bool cc_val = (fcsr >> shift) & 0x00000001;
 124     return cc_val;
 125 }
 126
 127 uint32_t
 128 genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
 129 {
 130     int cc_idx = (cc_num == 0) ? 23 : cc_num + 24;
 131
 132     fcsr = bits(fcsr, 31, cc_idx + 1) << (cc_idx + 1) |
 133            cc_val << cc_idx |
 134            bits(fcsr, cc_idx - 1, 0);
 135
 136     return fcsr;
 137 }
 138
 139 uint32_t
 140 genInvalidVector(uint32_t fcsr_bits)
 141 {
 142     //Set FCSR invalid in "flag" field
 143     int invalid_offset = Invalid + Flag_Field;
 144     fcsr_bits = fcsr_bits | (1 << invalid_offset);
 145
 146     //Set FCSR invalid in "cause" flag
 147     int cause_offset = Invalid + Cause_Field;
 148     fcsr_bits = fcsr_bits | (1 << cause_offset);
 149
 150     return fcsr_bits;
 151 }
 152
 153 bool
 154 isNan(void *val_ptr, int size)
 155 {
 156     switch (size)
 157     {
 158       case 32:
 159         {
 160             uint32_t val_bits = *(uint32_t *) val_ptr;
 161             return (bits(val_bits, 30, 23) == 0xFF);
 162         }
 163
 164       case 64:
 165         {
 166             uint64_t val_bits = *(uint64_t *) val_ptr;
 167             return (bits(val_bits, 62, 52) == 0x7FF);
 168         }
 169
 170       default:
 171         panic("Type unsupported. Size mismatch\n");
 172     }
 173 }
 174
 175
 176 bool
 177 isQnan(void *val_ptr, int size)
 178 {
 179     switch (size)
 180     {
 181       case 32:
 182         {
 183             uint32_t val_bits = *(uint32_t *) val_ptr;
 184             return (bits(val_bits, 30, 22) == 0x1FE);
 185         }
 186
 187       case 64:
 188         {
 189             uint64_t val_bits = *(uint64_t *) val_ptr;
 190             return (bits(val_bits, 62, 51) == 0xFFE);
 191         }
 192
 193       default:
 194         panic("Type unsupported. Size mismatch\n");
 195     }
 196 }
 197
 198 bool
 199 isSnan(void *val_ptr, int size)
 200 {
 201     switch (size)
 202     {
 203       case 32:
 204         {
 205             uint32_t val_bits = *(uint32_t *) val_ptr;
 206             return (bits(val_bits, 30, 22) == 0x1FF);
 207         }
 208
 209       case 64:
 210         {
 211             uint64_t val_bits = *(uint64_t *) val_ptr;
 212             return (bits(val_bits, 62, 51) == 0xFFF);
 213         }
 214
 215       default:
 216         panic("Type unsupported. Size mismatch\n");
 217     }
 218 }
 219
 220 template <class CPU>
 221 void
 222 zeroRegisters(CPU *cpu)
 223 {
 224     // Insure ISA semantics
 225     // (no longer very clean due to the change in setIntReg() in the
 226     // cpu model.  Consider changing later.)
 227     cpu->thread->setIntReg(ZeroReg, 0);
 228     cpu->thread->setFloatReg(ZeroReg, 0.0);
 229 }
 230
 231 void
 232 startupCPU(ThreadContext *tc, int cpuId)
 233 {
 234     tc->activate(Cycles(0));
 235 }
 236
 237 void
 238 initCPU(ThreadContext *tc, int cpuId)
 239 {}
 240
 241 void
 242 copyRegs(ThreadContext *src, ThreadContext *dest)
 243 {
 244     panic("Copy Regs Not Implemented Yet\n");
 245 }
 246
 247 void
 248 copyMiscRegs(ThreadContext *src, ThreadContext *dest)
 249 {
 250     panic("Copy Misc. Regs Not Implemented Yet\n");
 251 }
 252 void
 253 skipFunction(ThreadContext *tc)
 254 {
 255     TheISA::PCState newPC = tc->pcState();
 256     newPC.set(tc->readIntReg(ReturnAddressReg));
 257     tc->pcState(newPC);
 258 }
 259
 260
 261 } // namespace MipsISA