2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
33 #include "arch/mips/isa_traits.hh"
34 #include "arch/mips/utility.hh"
35 #include "base/bitfield.hh"
36 #include "base/misc.hh"
37 #include "config/full_system.hh"
38 #include "cpu/static_inst.hh"
39 #include "cpu/thread_context.hh"
40 #include "sim/serialize.hh"
42 #include "arch/mips/registers.hh"
43 #include "arch/mips/vtophys.hh"
44 #include "mem/vport.hh"
47 using namespace MipsISA
;
53 getArgument(ThreadContext
*tc
, int &number
, uint16_t size
, bool fp
)
55 panic("getArgument() not implemented\n");
60 fpConvert(ConvertType cvt_type
, double fp_val
)
65 case SINGLE_TO_DOUBLE
:
67 double sdouble_val
= fp_val
;
68 void *sdouble_ptr
= &sdouble_val
;
69 uint64_t sdp_bits
= *(uint64_t *) sdouble_ptr
;
75 int32_t sword_val
= (int32_t) fp_val
;
76 void *sword_ptr
= &sword_val
;
77 uint64_t sword_bits
= *(uint32_t *) sword_ptr
;
83 float wfloat_val
= fp_val
;
84 void *wfloat_ptr
= &wfloat_val
;
85 uint64_t wfloat_bits
= *(uint32_t *) wfloat_ptr
;
91 double wdouble_val
= fp_val
;
92 void *wdouble_ptr
= &wdouble_val
;
93 uint64_t wdp_bits
= *(uint64_t *) wdouble_ptr
;
98 panic("Invalid Floating Point Conversion Type (%d). See \"types.hh\" for List of Conversions\n",cvt_type
);
104 roundFP(double val
, int digits
)
106 double digit_offset
= pow(10.0,digits
);
107 val
= val
* digit_offset
;
110 val
= val
/ digit_offset
;
117 int trunc_val
= (int) val
;
118 return (double) trunc_val
;
122 getCondCode(uint32_t fcsr
, int cc_idx
)
124 int shift
= (cc_idx
== 0) ? 23 : cc_idx
+ 24;
125 bool cc_val
= (fcsr
>> shift
) & 0x00000001;
130 genCCVector(uint32_t fcsr
, int cc_num
, uint32_t cc_val
)
132 int cc_idx
= (cc_num
== 0) ? 23 : cc_num
+ 24;
134 fcsr
= bits(fcsr
, 31, cc_idx
+ 1) << (cc_idx
+ 1) |
136 bits(fcsr
, cc_idx
- 1, 0);
142 genInvalidVector(uint32_t fcsr_bits
)
144 //Set FCSR invalid in "flag" field
145 int invalid_offset
= Invalid
+ Flag_Field
;
146 fcsr_bits
= fcsr_bits
| (1 << invalid_offset
);
148 //Set FCSR invalid in "cause" flag
149 int cause_offset
= Invalid
+ Cause_Field
;
150 fcsr_bits
= fcsr_bits
| (1 << cause_offset
);
156 isNan(void *val_ptr
, int size
)
162 uint32_t val_bits
= *(uint32_t *) val_ptr
;
163 return (bits(val_bits
, 30, 23) == 0xFF);
168 uint64_t val_bits
= *(uint64_t *) val_ptr
;
169 return (bits(val_bits
, 62, 52) == 0x7FF);
173 panic("Type unsupported. Size mismatch\n");
179 isQnan(void *val_ptr
, int size
)
185 uint32_t val_bits
= *(uint32_t *) val_ptr
;
186 return (bits(val_bits
, 30, 22) == 0x1FE);
191 uint64_t val_bits
= *(uint64_t *) val_ptr
;
192 return (bits(val_bits
, 62, 51) == 0xFFE);
196 panic("Type unsupported. Size mismatch\n");
201 isSnan(void *val_ptr
, int size
)
207 uint32_t val_bits
= *(uint32_t *) val_ptr
;
208 return (bits(val_bits
, 30, 22) == 0x1FF);
213 uint64_t val_bits
= *(uint64_t *) val_ptr
;
214 return (bits(val_bits
, 62, 51) == 0xFFF);
218 panic("Type unsupported. Size mismatch\n");
224 zeroRegisters(CPU
*cpu
)
226 // Insure ISA semantics
227 // (no longer very clean due to the change in setIntReg() in the
228 // cpu model. Consider changing later.)
229 cpu
->thread
->setIntReg(ZeroReg
, 0);
230 cpu
->thread
->setFloatReg(ZeroReg
, 0.0);
234 startupCPU(ThreadContext
*tc
, int cpuId
)
236 tc
->activate(0/*tc->threadId()*/);
240 initCPU(ThreadContext
*tc
, int cpuId
)
244 copyRegs(ThreadContext
*src
, ThreadContext
*dest
)
246 panic("Copy Regs Not Implemented Yet\n");
250 copyMiscRegs(ThreadContext
*src
, ThreadContext
*dest
)
252 panic("Copy Misc. Regs Not Implemented Yet\n");
255 skipFunction(ThreadContext
*tc
)
257 TheISA::PCState newPC
= tc
->pcState();
258 newPC
.set(tc
->readIntReg(ReturnAddressReg
));
263 } // namespace MipsISA