2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
33 #include "arch/mips/isa_traits.hh"
34 #include "arch/mips/registers.hh"
35 #include "arch/mips/utility.hh"
36 #include "arch/mips/vtophys.hh"
37 #include "base/bitfield.hh"
38 #include "base/misc.hh"
39 #include "cpu/static_inst.hh"
40 #include "cpu/thread_context.hh"
41 #include "mem/fs_translating_port_proxy.hh"
42 #include "sim/serialize.hh"
45 using namespace MipsISA
;
51 getArgument(ThreadContext
*tc
, int &number
, uint16_t size
, bool fp
)
53 panic("getArgument() not implemented\n");
58 fpConvert(ConvertType cvt_type
, double fp_val
)
63 case SINGLE_TO_DOUBLE
:
65 double sdouble_val
= fp_val
;
66 void *sdouble_ptr
= &sdouble_val
;
67 uint64_t sdp_bits
= *(uint64_t *) sdouble_ptr
;
73 int32_t sword_val
= (int32_t) fp_val
;
74 void *sword_ptr
= &sword_val
;
75 uint64_t sword_bits
= *(uint32_t *) sword_ptr
;
81 float wfloat_val
= fp_val
;
82 void *wfloat_ptr
= &wfloat_val
;
83 uint64_t wfloat_bits
= *(uint32_t *) wfloat_ptr
;
89 double wdouble_val
= fp_val
;
90 void *wdouble_ptr
= &wdouble_val
;
91 uint64_t wdp_bits
= *(uint64_t *) wdouble_ptr
;
96 panic("Invalid Floating Point Conversion Type (%d). See \"types.hh\" for List of Conversions\n",cvt_type
);
102 roundFP(double val
, int digits
)
104 double digit_offset
= pow(10.0,digits
);
105 val
= val
* digit_offset
;
108 val
= val
/ digit_offset
;
115 int trunc_val
= (int) val
;
116 return (double) trunc_val
;
120 getCondCode(uint32_t fcsr
, int cc_idx
)
122 int shift
= (cc_idx
== 0) ? 23 : cc_idx
+ 24;
123 bool cc_val
= (fcsr
>> shift
) & 0x00000001;
128 genCCVector(uint32_t fcsr
, int cc_num
, uint32_t cc_val
)
130 int cc_idx
= (cc_num
== 0) ? 23 : cc_num
+ 24;
132 fcsr
= bits(fcsr
, 31, cc_idx
+ 1) << (cc_idx
+ 1) |
134 bits(fcsr
, cc_idx
- 1, 0);
140 genInvalidVector(uint32_t fcsr_bits
)
142 //Set FCSR invalid in "flag" field
143 int invalid_offset
= Invalid
+ Flag_Field
;
144 fcsr_bits
= fcsr_bits
| (1 << invalid_offset
);
146 //Set FCSR invalid in "cause" flag
147 int cause_offset
= Invalid
+ Cause_Field
;
148 fcsr_bits
= fcsr_bits
| (1 << cause_offset
);
154 isNan(void *val_ptr
, int size
)
160 uint32_t val_bits
= *(uint32_t *) val_ptr
;
161 return (bits(val_bits
, 30, 23) == 0xFF);
166 uint64_t val_bits
= *(uint64_t *) val_ptr
;
167 return (bits(val_bits
, 62, 52) == 0x7FF);
171 panic("Type unsupported. Size mismatch\n");
177 isQnan(void *val_ptr
, int size
)
183 uint32_t val_bits
= *(uint32_t *) val_ptr
;
184 return (bits(val_bits
, 30, 22) == 0x1FE);
189 uint64_t val_bits
= *(uint64_t *) val_ptr
;
190 return (bits(val_bits
, 62, 51) == 0xFFE);
194 panic("Type unsupported. Size mismatch\n");
199 isSnan(void *val_ptr
, int size
)
205 uint32_t val_bits
= *(uint32_t *) val_ptr
;
206 return (bits(val_bits
, 30, 22) == 0x1FF);
211 uint64_t val_bits
= *(uint64_t *) val_ptr
;
212 return (bits(val_bits
, 62, 51) == 0xFFF);
216 panic("Type unsupported. Size mismatch\n");
222 zeroRegisters(CPU
*cpu
)
224 // Insure ISA semantics
225 // (no longer very clean due to the change in setIntReg() in the
226 // cpu model. Consider changing later.)
227 cpu
->thread
->setIntReg(ZeroReg
, 0);
228 cpu
->thread
->setFloatReg(ZeroReg
, 0.0);
232 startupCPU(ThreadContext
*tc
, int cpuId
)
234 tc
->activate(Cycles(0));
238 initCPU(ThreadContext
*tc
, int cpuId
)
242 copyRegs(ThreadContext
*src
, ThreadContext
*dest
)
244 // First loop through the integer registers.
245 for (int i
= 0; i
< NumIntRegs
; i
++)
246 dest
->setIntRegFlat(i
, src
->readIntRegFlat(i
));
248 // Then loop through the floating point registers.
249 for (int i
= 0; i
< NumFloatRegs
; i
++)
250 dest
->setFloatRegFlat(i
, src
->readFloatRegFlat(i
));
252 // Would need to add condition-code regs if implemented
253 assert(NumCCRegs
== 0);
255 // Copy misc. registers
256 for (int i
= 0; i
< NumMiscRegs
; i
++)
257 dest
->setMiscRegNoEffect(i
, src
->readMiscRegNoEffect(i
));
259 // Copy over the PC State
260 dest
->pcState(src
->pcState());
264 copyMiscRegs(ThreadContext
*src
, ThreadContext
*dest
)
266 panic("Copy Misc. Regs Not Implemented Yet\n");
269 skipFunction(ThreadContext
*tc
)
271 TheISA::PCState newPC
= tc
->pcState();
272 newPC
.set(tc
->readIntReg(ReturnAddressReg
));
277 } // namespace MipsISA