src/arch/mips/utility.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * Copyright (c) 2007 MIPS Technologies, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 #ifndef __ARCH_MIPS_UTILITY_HH__
  31 #define __ARCH_MIPS_UTILITY_HH__
  32 #include "arch/mips/isa_traits.hh"
  33 #include "arch/mips/types.hh"
  34 #include "base/logging.hh"
  35 #include "base/types.hh"
  36 #include "cpu/static_inst.hh"
  37 #include "cpu/thread_context.hh"
  38
  39 class ThreadContext;
  40
  41 namespace MipsISA {
  42
  43 inline PCState
  44 buildRetPC(const PCState &curPC, const PCState &callPC)
  45 {
  46     PCState ret = callPC;
  47     ret.advance();
  48     ret.pc(curPC.npc());
  49     return ret;
  50 }
  51
  52 uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
  53
  54 ////////////////////////////////////////////////////////////////////////
  55 //
  56 // Floating Point Utility Functions
  57 //
  58 uint64_t fpConvert(ConvertType cvt_type, double fp_val);
  59 double roundFP(double val, int digits);
  60 double truncFP(double val);
  61
  62 bool getCondCode(uint32_t fcsr, int cc);
  63 uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val);
  64 uint32_t genInvalidVector(uint32_t fcsr);
  65
  66 bool isNan(void *val_ptr, int size);
  67 bool isQnan(void *val_ptr, int size);
  68 bool isSnan(void *val_ptr, int size);
  69
  70 static inline bool
  71 inUserMode(ThreadContext *tc)
  72 {
  73     RegVal Stat = tc->readMiscReg(MISCREG_STATUS);
  74     RegVal Dbg = tc->readMiscReg(MISCREG_DEBUG);
  75
  76     if ((Stat & 0x10000006) == 0 &&  // EXL, ERL or CU0 set, CP0 accessible
  77         (Dbg & 0x40000000) == 0 &&   // DM bit set, CP0 accessible
  78         (Stat & 0x00000018) != 0) {  // KSU = 0, kernel mode is base mode
  79         // Unable to use Status_CU0, etc directly, using bitfields & masks
  80         return true;
  81     } else {
  82         return false;
  83     }
  84 }
  85
  86 ////////////////////////////////////////////////////////////////////////
  87 //
  88 //  Translation stuff
  89 //
  90 inline Addr
  91 TruncPage(Addr addr)
  92 {
  93     return addr & ~(PageBytes - 1);
  94 }
  95
  96 inline Addr
  97 RoundPage(Addr addr)
  98 {
  99     return (addr + PageBytes - 1) & ~(PageBytes - 1);
 100 }
 101
 102 void copyRegs(ThreadContext *src, ThreadContext *dest);
 103 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
 104
 105 void skipFunction(ThreadContext *tc);
 106
 107 inline void
 108 advancePC(PCState &pc, const StaticInstPtr &inst)
 109 {
 110     pc.advance();
 111 }
 112
 113 inline uint64_t
 114 getExecutingAsid(ThreadContext *tc)
 115 {
 116     return 0;
 117 }
 118
 119 };
 120
 121
 122 #endif