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34 * Authors: Korey L. Sewell
37 #ifndef __ARCH_MIPS_UTILITY_HH__
38 #define __ARCH_MIPS_UTILITY_HH__
39 #include "config/full_system.hh"
40 #include "arch/mips/types.hh"
41 #include "arch/mips/isa_traits.hh"
42 #include "base/misc.hh"
43 #include "config/full_system.hh"
44 //XXX This is needed for size_t. We should use something other than size_t
45 //#include "kern/linux/linux.hh"
46 #include "sim/host.hh"
48 #include "cpu/thread_context.hh"
54 uint64_t getArgument(ThreadContext *tc, int number, bool fp);
56 //Floating Point Utility Functions
57 uint64_t fpConvert(ConvertType cvt_type, double fp_val);
58 double roundFP(double val, int digits);
59 double truncFP(double val);
61 bool getCondCode(uint32_t fcsr, int cc);
62 uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val);
63 uint32_t genInvalidVector(uint32_t fcsr);
65 bool isNan(void *val_ptr, int size);
66 bool isQnan(void *val_ptr, int size);
67 bool isSnan(void *val_ptr, int size);
69 void startupCPU(ThreadContext *tc, int cpuId);
72 inUserMode(ThreadContext *tc)
74 MiscReg Stat = tc->readMiscReg(MipsISA::Status);
75 MiscReg Dbg = tc->readMiscReg(MipsISA::Debug);
77 if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible
78 && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
79 && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode
80 // Unable to use Status_CU0, etc directly, using bitfields & masks
87 // Instruction address compression hooks
88 static inline Addr realPCToFetchPC(const Addr &addr) {
92 static inline Addr fetchPCToRealPC(const Addr &addr) {
96 // the size of "fetched" instructions (not necessarily the size
97 // of real instructions for PISA)
98 static inline size_t fetchInstSize() {
99 return sizeof(MachInst);
102 static inline MachInst makeRegisterCopy(int dest, int src) {
103 panic("makeRegisterCopy not implemented");
107 static inline int flattenFloatIndex(ThreadContext * tc, int reg)
112 int flattenIntIndex(ThreadContext * tc, int reg);
114 void copyRegs(ThreadContext *src, ThreadContext *dest);
116 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
120 void zeroRegisters(CPU *cpu);
122 ////////////////////////////////////////////////////////////////////////
127 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
130 inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
132 inline bool IsKSeg0(Addr a) { return KSeg0Base <= a && a <= KSeg0End; }
134 inline Addr KSeg02Phys(Addr addr) { return addr & KSeg0Mask; }
136 inline Addr KSeg12Phys(Addr addr) { return addr & KSeg1Mask; }
138 inline bool IsKSeg1(Addr a) { return KSeg1Base <= a && a <= KSeg1End; }
140 inline bool IsKSSeg(Addr a) { return KSSegBase <= a && a <= KSSegEnd; }
142 inline bool IsKSeg3(Addr a) { return KSeg3Base <= a && a <= KSeg3End; }
146 { return addr & ~(PageBytes - 1); }
150 { return (addr + PageBytes - 1) & ~(PageBytes - 1); }
152 void initCPU(ThreadContext *tc, int cpuId);
153 void initIPRs(ThreadContext *tc, int cpuId);
156 * Function to check for and process any interrupts.
157 * @param tc The thread context.
160 void processInterrupts(TC *tc);