src/arch/power/faults.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * Copyright (c) 2009 The University of Edinburgh
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 #ifndef __ARCH_POWER_FAULTS_HH__
  31 #define __ARCH_POWER_FAULTS_HH__
  32
  33 #include "cpu/thread_context.hh"
  34 #include "sim/faults.hh"
  35
  36 #define setbit(shift, mask) ( (uint64_t)1 << shift | mask)
  37 #define unsetbit(shift,mask) ( ~((uint64_t)1 << shift) & mask)
  38 #define setBitMask(shift) ( (uint64_t)1 << shift)
  39 #define unsetMask(start ,end)(~((setBitMask(start))-1) | ((setBitMask(end))-1))
  40
  41 enum pcSet
  42 {   DecrementerPCSet = 0x900,
  43     SystemCallPCSet = 0xC00,
  44     ProgramPCSet = 0x700,
  45     DataStoragePCSet = 0x300,
  46     InstrStoragePCSet = 0x400
  47 };
  48
  49 namespace PowerISA
  50 {
  51
  52 class PowerFaultBase : public FaultBase
  53 {
  54   protected:
  55     FaultName _name;
  56
  57     PowerFaultBase(FaultName name)
  58         : _name(name)
  59     {
  60     }
  61
  62     FaultName
  63     name() const
  64     {
  65         return _name;
  66     }
  67 };
  68
  69
  70 class UnimplementedOpcodeFault : public PowerFaultBase
  71 {
  72   public:
  73     UnimplementedOpcodeFault()
  74         : PowerFaultBase("Unimplemented Opcode")
  75     {
  76     }
  77 };
  78
  79
  80 class MachineCheckFault : public PowerFaultBase
  81 {
  82   public:
  83     MachineCheckFault()
  84         : PowerFaultBase("Machine Check")
  85     {
  86     }
  87 };
  88
  89
  90 class AlignmentFault : public PowerFaultBase
  91 {
  92   public:
  93     AlignmentFault()
  94         : PowerFaultBase("Alignment")
  95     {
  96     }
  97 };
  98
  99
 100 class PowerInterrupt : public PowerFaultBase
 101 {
 102   public:
 103     PowerInterrupt()
 104         : PowerFaultBase("Interrupt")
 105     {
 106     }
 107     virtual void updateMsr(ThreadContext * tc)
 108       {
 109         Msr msr = tc->readIntReg(INTREG_MSR);
 110         msr.tm = 0;
 111         msr.vec = 0;
 112         msr.vsx = 0;
 113         msr.fp = 0;
 114         msr.pr = 0;
 115         msr.pmm = 0;
 116         msr.ir = 0;
 117         msr.dr = 0;
 118         msr.fe1 = 0;
 119         msr.fe0 = 0;
 120         msr.ee = 0;
 121         msr.ri = 0;
 122         msr.te = 0;
 123         msr.sf = 1;
 124         msr = unsetbit(5, msr);
 125         tc->setIntReg(INTREG_MSR, msr);
 126       }
 127
 128     virtual void updateSRR1(ThreadContext *tc, uint64_t BitMask=0x0000000)
 129     {
 130       Msr msr = tc->readIntReg(INTREG_MSR);
 131       uint64_t srr1 = ((msr & unsetMask(31, 27)) & unsetMask(22,16)) | BitMask;
 132       tc->setIntReg(INTREG_SRR1, srr1);
 133     }
 134 };
 135
 136 };
 137
 138
 139 class DecrementerInterrupt : public PowerInterrupt
 140 {
 141   public:
 142     DecrementerInterrupt()
 143     {
 144     }
 145     virtual void invoke(ThreadContext * tc, const StaticInstPtr &inst =
 146                         StaticInst::nullStaticInstPtr)
 147     {
 148       // Refer Power ISA Manual v3.0B Book-III, section 6.5.11
 149       tc->setIntReg(INTREG_SRR0 , tc->instAddr());
 150       PowerInterrupt::updateSRR1(tc);
 151       PowerInterrupt::updateMsr(tc);
 152       tc->pcState(DecrementerPCSet);
 153     }
 154 };
 155
 156 } // namespace PowerISA
 157
 158 #endif // __ARCH_POWER_FAULTS_HH__