src/arch/power/insts/branch.cc

   1 /*
   2  * Copyright (c) 2009 The University of Edinburgh
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include "arch/power/insts/branch.hh"
  30
  31 #include "base/loader/symtab.hh"
  32 #include "cpu/thread_context.hh"
  33
  34 using namespace PowerISA;
  35
  36 const std::string &
  37 PCDependentDisassembly::disassemble(
  38         Addr pc, const Loader::SymbolTable *symtab) const
  39 {
  40     if (!cachedDisassembly ||
  41         pc != cachedPC || symtab != cachedSymtab)
  42     {
  43         if (cachedDisassembly)
  44             delete cachedDisassembly;
  45
  46         cachedDisassembly =
  47             new std::string(generateDisassembly(pc, symtab));
  48         cachedPC = pc;
  49         cachedSymtab = symtab;
  50     }
  51
  52     return *cachedDisassembly;
  53 }
  54
  55
  56 PowerISA::PCState
  57 BranchOp::branchTarget(const PowerISA::PCState &pc) const
  58 {
  59     if (aaSet) {
  60         return disp;
  61     } else {
  62         return pc.pc() + disp;
  63     }
  64 }
  65
  66
  67 std::string
  68 BranchOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
  69 {
  70     std::stringstream ss;
  71     Addr target;
  72
  73     // Generate correct mnemonic
  74     std::string myMnemonic(mnemonic);
  75
  76     // Additional characters depending on isa bits being set
  77     if (lkSet) myMnemonic = myMnemonic + "l";
  78     if (aaSet) myMnemonic = myMnemonic + "a";
  79     ccprintf(ss, "%-10s ", myMnemonic);
  80
  81     if (aaSet) {
  82         target = disp;
  83     } else {
  84         target = pc + disp;
  85     }
  86
  87     Loader::SymbolTable::const_iterator it;
  88     if (symtab && (it = symtab->find(target)) != symtab->end())
  89         ss << it->name;
  90     else
  91         ccprintf(ss, "%#x", target);
  92
  93     return ss.str();
  94 }
  95
  96
  97 PowerISA::PCState
  98 BranchDispCondOp::branchTarget(const PowerISA::PCState &pc) const
  99 {
 100     if (aaSet) {
 101         return disp;
 102     } else {
 103         return pc.pc() + disp;
 104     }
 105 }
 106
 107
 108 std::string
 109 BranchDispCondOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 110 {
 111     std::stringstream ss;
 112     Addr target;
 113
 114     // Generate the correct mnemonic
 115     std::string myMnemonic(mnemonic);
 116
 117     // Additional characters depending on isa bits being set
 118     if (lkSet) myMnemonic = myMnemonic + "l";
 119     if (aaSet) myMnemonic = myMnemonic + "a";
 120     ccprintf(ss, "%-10s ", myMnemonic);
 121
 122     // Print BI and BO fields
 123     ss << crBit << ", " << opts << ", ";
 124
 125     if (aaSet) {
 126         target = disp;
 127     } else {
 128         target = pc + disp;
 129     }
 130
 131     Loader::SymbolTable::const_iterator it;
 132     if (symtab && (it = symtab->find(target)) != symtab->end())
 133         ss << it->name;
 134     else
 135         ccprintf(ss, "%#x", target);
 136
 137     return ss.str();
 138 }
 139
 140
 141 PowerISA::PCState
 142 BranchRegCondOp::branchTarget(ThreadContext *tc) const
 143 {
 144     Addr addr = tc->readIntReg(_srcRegIdx[_numSrcRegs - 1].index());
 145     return addr & -4ULL;
 146 }
 147
 148
 149 std::string
 150 BranchRegCondOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 151 {
 152     std::stringstream ss;
 153
 154     // Generate the correct mnemonic
 155     std::string myMnemonic(mnemonic);
 156
 157     // Additional characters depending on isa bits being set
 158     if (lkSet) myMnemonic = myMnemonic + "l";
 159     ccprintf(ss, "%-10s ", mnemonic);
 160
 161     // Print the BI and BO fields
 162     ss << crBit << ", " << opts;
 163
 164     return ss.str();
 165 }