src/arch/power/insts/mem.cc

   1 /*
   2  * Copyright (c) 2009 The University of Edinburgh
   3  * Copyright (c) 2021 IBM Corporation
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 #include "arch/power/insts/mem.hh"
  31
  32 #include "base/loader/symtab.hh"
  33
  34 using namespace PowerISA;
  35
  36 std::string
  37 MemOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
  38 {
  39     return csprintf("%-10s", mnemonic);
  40 }
  41
  42
  43 std::string
  44 MemDispOp::generateDisassembly(
  45         Addr pc, const Loader::SymbolTable *symtab) const
  46 {
  47     std::stringstream ss;
  48
  49     ccprintf(ss, "%-10s ", mnemonic);
  50
  51     // Print the destination only for a load
  52     if (!flags[IsStore]) {
  53         if (_numDestRegs > 0) {
  54
  55             // If the instruction updates the source register with the
  56             // EA, then this source register is placed in position 0,
  57             // therefore we print the last destination register.
  58             printReg(ss, destRegIdx(_numDestRegs-1));
  59         }
  60     }
  61
  62     // Print the data register for a store
  63     else {
  64         if (_numSrcRegs > 0) {
  65             printReg(ss, srcRegIdx(0));
  66         }
  67     }
  68
  69     // Print the displacement
  70     ss << ", " << disp;
  71     ss << "(";
  72
  73     // Print the address register for a load
  74     if (!flags[IsStore]) {
  75         if (_numSrcRegs > 0) {
  76             printReg(ss, srcRegIdx(0));
  77         }
  78
  79         // The address register is skipped if it is R0
  80         else {
  81             ss << "0";
  82         }
  83     }
  84
  85     // Print the address register for a store
  86     else {
  87         if (_numSrcRegs > 1) {
  88             printReg(ss, srcRegIdx(1));
  89         }
  90
  91         // The address register is skipped if it is R0
  92         else {
  93             ss << "0";
  94         }
  95     }
  96
  97     ss << ")";
  98
  99     return ss.str();
 100 }
 101
 102
 103 std::string
 104 MemDispShiftOp::generateDisassembly(
 105         Addr pc, const Loader::SymbolTable *symtab) const
 106 {
 107     std::stringstream ss;
 108
 109     ccprintf(ss, "%-10s ", mnemonic);
 110
 111     // Print the destination only for a load
 112     if (!flags[IsStore]) {
 113         if (_numDestRegs > 0) {
 114
 115             // If the instruction updates the source register with the
 116             // EA, then this source register is placed in position 0,
 117             // therefore we print the last destination register.
 118             printReg(ss, destRegIdx(_numDestRegs-1));
 119         }
 120     }
 121
 122     // Print the data register for a store
 123     else {
 124         if (_numSrcRegs > 0) {
 125             printReg(ss, srcRegIdx(0));
 126         }
 127     }
 128
 129     // Print the displacement
 130     ss << ", " << (disp << 2);
 131     ss << "(";
 132
 133     // Print the address register for a load
 134     if (!flags[IsStore]) {
 135         if (_numSrcRegs > 0) {
 136             printReg(ss, srcRegIdx(0));
 137         }
 138
 139         // The address register is skipped if it is R0
 140         else {
 141             ss << "0";
 142         }
 143     }
 144
 145     // Print the address register for a store
 146     else {
 147         if (_numSrcRegs > 1) {
 148             printReg(ss, srcRegIdx(1));
 149         }
 150
 151         // The address register is skipped if it is R0
 152         else {
 153             ss << "0";
 154         }
 155     }
 156
 157     ss << ")";
 158
 159     return ss.str();
 160 }
 161
 162
 163 std::string
 164 MemIndexOp::generateDisassembly(
 165         Addr pc, const Loader::SymbolTable *symtab) const
 166 {
 167     std::stringstream ss;
 168
 169     ccprintf(ss, "%-10s ", mnemonic);
 170
 171     // Print the destination only for a load
 172     if (!flags[IsStore]) {
 173         if (_numDestRegs > 0) {
 174
 175             // If the instruction updates the source register with the
 176             // EA, then this source register is placed in position 0,
 177             // therefore we print the last destination register.
 178             printReg(ss, destRegIdx(_numDestRegs-1));
 179         }
 180     }
 181
 182     // Print the data register for a store
 183     else {
 184         if (_numSrcRegs > 0) {
 185             printReg(ss, srcRegIdx(0));
 186         }
 187     }
 188
 189     ss << ", ";
 190
 191     // Print the address registers for a load
 192     if (!flags[IsStore]) {
 193         if (_numSrcRegs > 1) {
 194             printReg(ss, srcRegIdx(0));
 195             ss << ", ";
 196             printReg(ss, srcRegIdx(1));
 197         }
 198
 199         // The first address register is skipped if it is R0
 200         else if (_numSrcRegs > 0) {
 201             ss << "0, ";
 202             printReg(ss, srcRegIdx(0));
 203         }
 204     }
 205
 206     // Print the address registers for a store
 207     else {
 208         if (_numSrcRegs > 2) {
 209             printReg(ss, srcRegIdx(1));
 210             ss << ", ";
 211             printReg(ss, srcRegIdx(2));
 212         }
 213
 214         // The first address register is skipped if it is R0
 215         else if (_numSrcRegs > 1) {
 216             ss << "0, ";
 217             printReg(ss, srcRegIdx(1));
 218         }
 219     }
 220
 221     return ss.str();
 222 }