arch-power: Add fields for VA form instructions
[gem5.git] / src / arch / power / isa / bitfields.isa
1 // -*- mode:c++ -*-
2
3 // Copyright (c) 2009 The University of Edinburgh
4 // All rights reserved.
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28
29 ////////////////////////////////////////////////////////////////////
30 //
31 // Bitfield definitions.
32 //
33 // The endianness is the opposite to what's used here, so things
34 // are reversed sometimes. Not sure of a fix to this though...
35
36 // Opcode fields
37 def bitfield PO <31:26>;
38 def bitfield A_XO <5:1>;
39 def bitfield DS_XO <1:0>;
40 def bitfield DX_XO <5:1>;
41 def bitfield VA_XO <5:0>;
42 def bitfield X_XO <10:1>;
43 def bitfield XFL_XO <10:1>;
44 def bitfield XFX_XO <10:1>;
45 def bitfield XL_XO <10:1>;
46 def bitfield XO_XO <9:1>;
47
48 // Register fields
49 def bitfield RA <20:16>;
50 def bitfield RB <15:11>;
51 def bitfield RC <10:6>;
52 def bitfield RS <25:21>;
53 def bitfield RT <25:21>;
54 def bitfield FRA <20:16>;
55 def bitfield FRB <15:11>;
56 def bitfield FRC <10:6>;
57 def bitfield FRS <25:21>;
58 def bitfield FRT <25:21>;
59
60 // The record bit can be in two positions
61 // Used to enable setting of the condition register
62 def bitfield RC31 <0>;
63 def bitfield RC21 <10>;
64
65 // Used to enable setting of the overflow flags
66 def bitfield OE <10>;
67
68 // SPR field for mtspr instruction
69 def bitfield SPR <20:11>;
70
71 // FXM field for mtcrf instruction
72 def bitfield FXM <19:12>;
73
74 // Branch fields
75 def bitfield BO <25:21>;
76 def bitfield LK <0>;
77 def bitfield AA <1>;
78
79 // Specifies a CR or FPSCR field
80 def bitfield BF <25:23>;
81
82 // Fields for FPSCR manipulation instructions
83 def bitfield FLM <24:17>;
84 // Named so to avoid conflicts with potential template typenames
85 def bitfield L_FIELD <25>;
86 // Named so to avoid conflicts with range_map.hh
87 def bitfield W_FIELD <16>;
88 // Named so to avoid conflicts with range.hh
89 def bitfield U_FIELD <15:12>;
90
91 // Field for specifying a bit in CR or FPSCR
92 def bitfield BT <25:21>;