src/arch/power/isa/bitfields.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2009 The University of Edinburgh
   4 // All rights reserved.
   5 //
   6 // Redistribution and use in source and binary forms, with or without
   7 // modification, are permitted provided that the following conditions are
   8 // met: redistributions of source code must retain the above copyright
   9 // notice, this list of conditions and the following disclaimer;
  10 // redistributions in binary form must reproduce the above copyright
  11 // notice, this list of conditions and the following disclaimer in the
  12 // documentation and/or other materials provided with the distribution;
  13 // neither the name of the copyright holders nor the names of its
  14 // contributors may be used to endorse or promote products derived from
  15 // this software without specific prior written permission.
  16 //
  17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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  27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28
  29 ////////////////////////////////////////////////////////////////////
  30 //
  31 // Bitfield definitions.
  32 //
  33 // The endianness is the opposite to what's used here, so things
  34 // are reversed sometimes. Not sure of a fix to this though...
  35
  36 // Opcode fields
  37 def bitfield OPCODE        <31:26>;
  38 def bitfield X_XO          <10:0>;
  39 def bitfield XO_XO         <10:1>;
  40 def bitfield A_XO          <5:1>;
  41
  42 // Register fields
  43 def bitfield RA            <20:16>;
  44 def bitfield RB            <15:11>;
  45 def bitfield RS            <25:21>;
  46 def bitfield RT            <25:21>;
  47 def bitfield FRA           <20:16>;
  48 def bitfield FRB           <15:11>;
  49 def bitfield FRC           <10:6>;
  50 def bitfield FRS           <25:21>;
  51 def bitfield FRT           <25:21>;
  52
  53 // The record bit can be in two positions
  54 // Used to enable setting of the condition register
  55 def bitfield RC31          <0>;
  56 def bitfield RC21          <10>;
  57
  58 // Used to enable setting of the overflow flags
  59 def bitfield OE            <10>;
  60
  61 // SPR field for mtspr instruction
  62 def bitfield SPR           <20:11>;
  63
  64 // FXM field for mtcrf instruction
  65 def bitfield FXM           <19:12>;
  66
  67 // Branch fields
  68 def bitfield LK            <0>;
  69 def bitfield AA            <1>;
  70
  71 // Specifies a CR or FPSCR field
  72 def bitfield BF            <25:23>;
  73
  74 // Fields for FPSCR manipulation instructions
  75 def bitfield FLM           <24:17>;
  76 // Named so to avoid conflicts with potential template typenames
  77 def bitfield L_FIELD       <25>;
  78 // Named so to avoid conflicts with range_map.hh
  79 def bitfield W_FIELD       <16>;
  80 // Named so to avoid conflicts with range.hh
  81 def bitfield U_FIELD       <15:12>;
  82
  83 // Field for specifying a bit in CR or FPSCR
  84 def bitfield BT            <25:21>;