src/arch/power/isa/decoder.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2009 The University of Edinburgh
   4 // All rights reserved.
   5 //
   6 // Redistribution and use in source and binary forms, with or without
   7 // modification, are permitted provided that the following conditions are
   8 // met: redistributions of source code must retain the above copyright
   9 // notice, this list of conditions and the following disclaimer;
  10 // redistributions in binary form must reproduce the above copyright
  11 // notice, this list of conditions and the following disclaimer in the
  12 // documentation and/or other materials provided with the distribution;
  13 // neither the name of the copyright holders nor the names of its
  14 // contributors may be used to endorse or promote products derived from
  15 // this software without specific prior written permission.
  16 //
  17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28
  29 ////////////////////////////////////////////////////////////////////
  30 //
  31 // The actual Power ISA decoder
  32 // ------------------------------
  33 //
  34 // I've used the Power ISA Book I v2.06 for instruction formats,
  35 // opcode numbers, register names, etc.
  36 //
  37 decode PO default Unknown::unknown() {
  38
  39     18: decode AA {
  40
  41         // Unconditionally branch relative to PC.
  42         format BranchPCRel {
  43             0: b({{ NIA = (uint32_t)(CIA + disp); }});
  44         }
  45
  46         // Unconditionally branch to fixed address.
  47         format BranchNonPCRel {
  48             1: ba({{ NIA = targetAddr; }});
  49         }
  50     }
  51
  52     16: decode AA {
  53
  54         // Conditionally branch relative to PC based on CR and CTR.
  55         format BranchPCRelCondCtr {
  56             0: bc({{ NIA = (uint32_t)(CIA + disp); }});
  57         }
  58
  59         // Conditionally branch to fixed address based on CR and CTR.
  60         format BranchNonPCRelCondCtr {
  61             1: bca({{ NIA = targetAddr; }});
  62         }
  63     }
  64
  65     19: decode XL_XO {
  66
  67         // Conditionally branch to address in LR based on CR and CTR.
  68         format BranchLrCondCtr {
  69            16: bclr({{ NIA = LR & 0xfffffffc; }});
  70         }
  71
  72         // Conditionally branch to address in CTR based on CR.
  73         format BranchCtrCond {
  74            528: bcctr({{ NIA = CTR & 0xfffffffc; }});
  75         }
  76
  77         // Condition register manipulation instructions.
  78         format CondLogicOp {
  79             257: crand({{
  80                 uint32_t crBa = bits(CR, 31 - ba);
  81                 uint32_t crBb = bits(CR, 31 - bb);
  82                 CR = insertBits(CR, 31 - bt, crBa & crBb);
  83             }});
  84
  85             449: cror({{
  86                 uint32_t crBa = bits(CR, 31 - ba);
  87                 uint32_t crBb = bits(CR, 31 - bb);
  88                 CR = insertBits(CR, 31 - bt, crBa | crBb);
  89             }});
  90
  91             255: crnand({{
  92                 uint32_t crBa = bits(CR, 31 - ba);
  93                 uint32_t crBb = bits(CR, 31 - bb);
  94                 CR = insertBits(CR, 31 - bt, !(crBa & crBb));
  95             }});
  96
  97             193: crxor({{
  98                 uint32_t crBa = bits(CR, 31 - ba);
  99                 uint32_t crBb = bits(CR, 31 - bb);
 100                 CR = insertBits(CR, 31 - bt, crBa ^ crBb);
 101             }});
 102
 103             33: crnor({{
 104                 uint32_t crBa = bits(CR, 31 - ba);
 105                 uint32_t crBb = bits(CR, 31 - bb);
 106                 CR = insertBits(CR, 31 - bt, !(crBa | crBb));
 107             }});
 108
 109             289: creqv({{
 110                 uint32_t crBa = bits(CR, 31 - ba);
 111                 uint32_t crBb = bits(CR, 31 - bb);
 112                 CR = insertBits(CR, 31 - bt, crBa == crBb);
 113             }});
 114
 115             129: crandc({{
 116                 uint32_t crBa = bits(CR, 31 - ba);
 117                 uint32_t crBb = bits(CR, 31 - bb);
 118                 CR = insertBits(CR, 31 - bt, crBa & !crBb);
 119             }});
 120
 121             417: crorc({{
 122                 uint32_t crBa = bits(CR, 31 - ba);
 123                 uint32_t crBb = bits(CR, 31 - bb);
 124                 CR = insertBits(CR, 31 - bt, crBa | !crBb);
 125             }});
 126         }
 127
 128         format CondMoveOp {
 129             0: mcrf({{
 130                 uint32_t crBfa = bits(CR, 31 - bfa*4, 28 - bfa*4);
 131                 CR = insertBits(CR, 31 - bf*4, 28 - bf*4, crBfa);
 132             }});
 133         }
 134
 135         format MiscOp {
 136             150: isync({{ }}, [ IsSerializeAfter ]);
 137         }
 138     }
 139
 140     17: IntOp::sc({{ xc->syscall(R0, &fault); }},
 141                   [ IsSyscall, IsNonSpeculative, IsSerializeAfter ]);
 142
 143     format LoadDispOp {
 144         34: lbz({{ Rt = Mem_ub; }});
 145         40: lhz({{ Rt = Mem_uh; }});
 146         42: lha({{ Rt = Mem_sh; }});
 147         32: lwz({{ Rt = Mem_uw; }});
 148     }
 149
 150     58: decode DS_XO {
 151         format LoadDispShiftOp {
 152             2: lwa({{ Rt = Mem_sw; }});
 153             0: ld({{ Rt = Mem; }});
 154         }
 155
 156         format LoadDispShiftUpdateOp {
 157             1: ldu({{ Rt = Mem; }});
 158         }
 159     }
 160
 161     62: decode DS_XO {
 162         format StoreDispShiftOp {
 163             0: std({{ Mem = Rs; }});
 164         }
 165
 166         format StoreDispShiftUpdateOp {
 167             1: stdu({{ Mem = Rs; }});
 168         }
 169     }
 170
 171     format LoadDispUpdateOp {
 172         35: lbzu({{ Rt = Mem_ub; }});
 173         41: lhzu({{ Rt = Mem_uh; }});
 174         43: lhau({{ Rt = Mem_sh; }});
 175         33: lwzu({{ Rt = Mem_uw; }});
 176     }
 177
 178     format StoreDispOp {
 179         38: stb({{ Mem_ub = Rs_ub; }});
 180         44: sth({{ Mem_uh = Rs_uh; }});
 181         36: stw({{ Mem = Rs_uw; }});
 182     }
 183
 184     format StoreDispUpdateOp {
 185         39: stbu({{ Mem_ub = Rs_ub; }});
 186         45: sthu({{ Mem_uh = Rs_uh; }});
 187         37: stwu({{ Mem = Rs_uw; }});
 188     }
 189
 190     format IntImmArithCheckRaOp {
 191         14: addi({{ Rt = Ra + imm; }},
 192                  {{ Rt = imm }});
 193
 194         15: addis({{ Rt = Ra + (imm << 16); }},
 195                   {{ Rt = imm << 16; }});
 196     }
 197
 198     format IntImmArithOp {
 199         12: addic({{ uint32_t src = Ra; Rt = src + imm; }},
 200                   [computeCA]);
 201
 202         13: addic_({{ uint32_t src = Ra; Rt = src + imm; }},
 203                    [computeCA, computeCR0]);
 204
 205         8: subfic({{ int32_t src = ~Ra; Rt = src + imm + 1; }},
 206                   [computeCA]);
 207
 208         7: mulli({{
 209             int32_t src = Ra_sw;
 210             int64_t prod = src * imm;
 211             Rt = (uint32_t)prod;
 212         }});
 213     }
 214
 215     format IntImmOp {
 216         10: cmpli({{
 217             Xer xer = XER;
 218             uint32_t cr = makeCRField(Ra, (uint32_t)uimm, xer.so);
 219             CR = insertCRField(CR, BF, cr);
 220             }});
 221         11: cmpi({{
 222             Xer xer = XER;
 223             uint32_t cr = makeCRField(Ra_sw, (int32_t)imm, xer.so);
 224             CR = insertCRField(CR, BF, cr);
 225             }});
 226     }
 227
 228     format IntImmLogicOp {
 229         24: ori({{ Ra = Rs | uimm; }});
 230         25: oris({{ Ra = Rs | (uimm << 16); }});
 231         26: xori({{ Ra = Rs ^ uimm; }});
 232         27: xoris({{ Ra = Rs ^ (uimm << 16); }});
 233         28: andi_({{ Ra = Rs & uimm; }},
 234                   true);
 235         29: andis_({{ Ra = Rs & (uimm << 16); }},
 236                    true);
 237     }
 238
 239     format IntRotateOp {
 240         21: rlwinm({{ Ra = rotateValue(Rs, sh) & fullMask; }});
 241         23: rlwnm({{ Ra = rotateValue(Rs, Rb) & fullMask; }});
 242         20: rlwimi({{ Ra = (rotateValue(Rs, sh) & fullMask) |
 243                            (Ra & ~fullMask); }});
 244     }
 245
 246     // There are a large number of instructions that have the same primary
 247     // opcode (PO) of 31. In this case, the instructions are of different
 248     // forms. For every form, the XO fields may vary in position and width.
 249     // The X, XFL, XFX and XL form instructions use bits 21 - 30 and the
 250     // XO form instructions use bits 22 - 30 as extended opcode (XO). To
 251     // avoid conflicts, instructions of each form have to be defined under
 252     // separate decode blocks. However, only a single decode block can be
 253     // associated with a particular PO and it will recognize only one type
 254     // of XO field. A solution for associating decode blocks for the other
 255     // types of XO fields with the same PO is to have the other blocks as
 256     // nested default cases.
 257     31: decode X_XO {
 258
 259         // All loads with an index register. The non-update versions
 260         // all use the value 0 if Ra == R0, not the value contained in
 261         // R0. Others update Ra with the effective address. In all cases,
 262         // Ra and Rb are source registers, Rt is the destintation.
 263         format LoadIndexOp {
 264             87: lbzx({{ Rt = Mem_ub; }});
 265             279: lhzx({{ Rt = Mem_uh; }});
 266             343: lhax({{ Rt = Mem_sh; }});
 267             790: lhbrx({{ Rt = swap_byte(Mem_uh); }});
 268             23: lwzx({{ Rt = Mem_uw; }});
 269             341: lwax({{ Rt = Mem_sw; }});
 270             20: lwarx({{ Rt = Mem_uw; Rsv = 1; RsvLen = 4; RsvAddr = EA; }});
 271             534: lwbrx({{ Rt = swap_byte(Mem_uw); }});
 272             21: ldx({{ Rt = Mem; }});
 273             532: ldbrx({{ Rt = swap_byte(Mem); }});
 274             535: lfsx({{ Ft_sf = Mem_sf; }});
 275             599: lfdx({{ Ft = Mem_df; }});
 276             855: lfiwax({{ Ft_uw = Mem; }});
 277         }
 278
 279         format LoadIndexUpdateOp {
 280             119: lbzux({{ Rt = Mem_ub; }});
 281             311: lhzux({{ Rt = Mem_uh; }});
 282             375: lhaux({{ Rt = Mem_sh; }});
 283             55: lwzux({{ Rt = Mem_uw; }});
 284             373: lwaux({{ Rt = Mem_sw; }});
 285             53: ldux({{ Rt = Mem; }});
 286             567: lfsux({{ Ft_sf = Mem_sf; }});
 287             631: lfdux({{ Ft = Mem_df; }});
 288         }
 289
 290         format StoreIndexOp {
 291             215: stbx({{ Mem_ub = Rs_ub; }});
 292             407: sthx({{ Mem_uh = Rs_uh; }});
 293             918: sthbrx({{ Mem_uh = swap_byte(Rs_uh); }});
 294             151: stwx({{ Mem_uw = Rs_uw; }});
 295             150: stwcx({{
 296                 bool store_performed = false;
 297                 Mem_uw = Rs_uw;
 298                 if (Rsv) {
 299                     if (RsvLen == 4) {
 300                         if (RsvAddr == EA) {
 301                             store_performed = true;
 302                         }
 303                     }
 304                 }
 305                 Xer xer = XER;
 306                 Cr cr = CR;
 307                 cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
 308                 CR = cr;
 309                 Rsv = 0;
 310             }});
 311             662: stwbrx({{ Mem_uw = swap_byte(Rs_uw); }});
 312             149: stdx({{ Mem = Rs }});
 313             660: stdbrx({{ Mem = swap_byte(Rs); }});
 314         }
 315
 316         format StoreIndexUpdateOp {
 317             247: stbux({{ Mem_ub = Rs_ub; }});
 318             439: sthux({{ Mem_uh = Rs_uh; }});
 319             183: stwux({{ Mem_uw = Rs_uw; }});
 320             181: stdux({{ Mem = Rs; }});
 321         }
 322
 323         format IntOp {
 324             0: cmp({{
 325                 Xer xer = XER;
 326                 uint32_t cr = makeCRField(Ra_sw, Rb_sw, xer.so);
 327                 CR = insertCRField(CR, BF, cr);
 328             }});
 329
 330             32: cmpl({{
 331                 Xer xer = XER;
 332                 uint32_t cr = makeCRField(Ra, Rb, xer.so);
 333                 CR = insertCRField(CR, BF, cr);
 334             }});
 335         }
 336
 337         // Integer logic instructions use source registers Rs and Rb,
 338         // with destination register Ra.
 339         format IntLogicOp {
 340             28: and({{ Ra = Rs & Rb; }});
 341             316: xor({{ Ra = Rs ^ Rb; }});
 342             476: nand({{ Ra = ~(Rs & Rb); }});
 343             444: or({{ Ra = Rs | Rb; }});
 344             124: nor({{ Ra = ~(Rs | Rb); }});
 345             60: andc({{ Ra = Rs & ~Rb; }});
 346             954: extsb({{ Ra = sext<8>(Rs); }});
 347             284: eqv({{ Ra = ~(Rs ^ Rb); }});
 348             412: orc({{ Ra = Rs | ~Rb; }});
 349             922: extsh({{ Ra = sext<16>(Rs); }});
 350             26: cntlzw({{ Ra = Rs == 0 ? 32 : 31 - findMsbSet(Rs); }});
 351             508: cmpb({{
 352                 uint32_t val = 0;
 353                 for (int n = 0; n < 32; n += 8) {
 354                     if(bits(Rs, n+7, n) == bits(Rb, n+7, n)) {
 355                         val = insertBits(val, n+7, n, 0xff);
 356                     }
 357                 }
 358                 Ra = val;
 359             }});
 360
 361             24: slw({{
 362                 if (Rb & 0x20) {
 363                     Ra = 0;
 364                 } else {
 365                     Ra = Rs << (Rb & 0x1f);
 366                 }
 367             }});
 368
 369             536: srw({{
 370                 if (Rb & 0x20) {
 371                     Ra = 0;
 372                 } else  {
 373                     Ra = Rs >> (Rb & 0x1f);
 374                 }
 375             }});
 376
 377             792: sraw({{
 378                 bool shiftSetCA = false;
 379                 int32_t s = Rs;
 380                 if (Rb == 0) {
 381                     Ra = Rs;
 382                     shiftSetCA = true;
 383                 } else if (Rb & 0x20) {
 384                     if (s < 0) {
 385                         Ra = (uint32_t)-1;
 386                         if (s & 0x7fffffff) {
 387                             shiftSetCA = true;
 388                         } else {
 389                             shiftSetCA = false;
 390                         }
 391                     } else {
 392                         Ra = 0;
 393                         shiftSetCA = false;
 394                     }
 395                 } else {
 396                     Ra = s >> (Rb & 0x1f);
 397                     if (s < 0 && (s << (32 - (Rb & 0x1f))) != 0) {
 398                         shiftSetCA = true;
 399                     } else {
 400                         shiftSetCA = false;
 401                     }
 402                 }
 403                 Xer xer1 = XER;
 404                 if (shiftSetCA) {
 405                     xer1.ca = 1;
 406                 } else {
 407                     xer1.ca = 0;
 408                 }
 409                 XER = xer1;
 410             }});
 411         }
 412
 413         // Integer logic instructions with a shift value.
 414         format IntShiftOp {
 415             824: srawi({{
 416                 bool shiftSetCA = false;
 417                 if (sh == 0) {
 418                     Ra = Rs;
 419                     shiftSetCA = false;
 420                 } else {
 421                     int32_t s = Rs;
 422                     Ra = s >> sh;
 423                     if (s < 0 && (s << (32 - sh)) != 0) {
 424                         shiftSetCA = true;
 425                     } else {
 426                         shiftSetCA = false;
 427                     }
 428                 }
 429                 Xer xer1 = XER;
 430                 if (shiftSetCA) {
 431                     xer1.ca = 1;
 432                 } else {
 433                     xer1.ca = 0;
 434                 }
 435                 XER = xer1;
 436             }});
 437         }
 438
 439         // Generic integer format instructions.
 440         format IntOp {
 441             339: decode SPR {
 442                 0x20: mfxer({{ Rt = XER; }});
 443                 0x100: mflr({{ Rt = LR; }});
 444                 0x120: mfctr({{ Rt = CTR; }});
 445             }
 446             467: decode SPR {
 447                 0x20: mtxer({{ XER = Rs; }});
 448                 0x100: mtlr({{ LR = Rs; }});
 449                 0x120: mtctr({{ CTR = Rs; }});
 450             }
 451         }
 452
 453         format StoreIndexOp {
 454             663: stfsx({{ Mem_sf = Fs_sf; }});
 455             727: stfdx({{ Mem_df = Fs; }});
 456             983: stfiwx({{ Mem = Fs_uw; }});
 457         }
 458
 459         format StoreIndexUpdateOp {
 460             695: stfsux({{ Mem_sf = Fs_sf; }});
 461             759: stfdux({{ Mem_df = Fs; }});
 462         }
 463
 464         // These instructions all provide data cache hints
 465         format MiscOp {
 466             278: dcbt({{ }});
 467             246: dcbtst({{ }});
 468             598: sync({{ }}, [ IsMemBarrier ]);
 469             854: eieio({{ }}, [ IsMemBarrier ]);
 470         }
 471
 472         // These instructions are of XO form with bit 21 as the OE bit.
 473         default: decode XO_XO {
 474
 475             // These instructions can all be reduced to the form
 476             // Rt = src1 + src2 [+ CA], therefore we just give src1 and src2
 477             // (and, if necessary, CA) definitions and let the python script
 478             // deal with setting things up correctly. We also give flags to
 479             // say which control registers to set.
 480             format IntSumOp {
 481                 266: add({{ Ra }}, {{ Rb }});
 482                 40: subf({{ ~Ra }}, {{ Rb }}, {{ 1 }});
 483                 10: addc({{ Ra }}, {{ Rb }},
 484                          computeCA = true);
 485                 8: subfc({{ ~Ra }}, {{ Rb }}, {{ 1 }},
 486                          true);
 487                 104: neg({{ ~Ra }}, {{ 1 }});
 488                 138: adde({{ Ra }}, {{ Rb }}, {{ xer.ca }},
 489                           true);
 490                 234: addme({{ Ra }}, {{ (uint32_t)-1 }}, {{ xer.ca }},
 491                            true);
 492                 136: subfe({{ ~Ra }}, {{ Rb }}, {{ xer.ca }},
 493                            true);
 494                 232: subfme({{ ~Ra }}, {{ (uint32_t)-1 }}, {{ xer.ca }},
 495                             true);
 496                 202: addze({{ Ra }}, {{ xer.ca }},
 497                            computeCA = true);
 498                 200: subfze({{ ~Ra }}, {{ xer.ca }},
 499                             computeCA = true);
 500             }
 501
 502             // Arithmetic instructions all use source registers Ra and Rb,
 503             // with destination register Rt.
 504             format IntArithOp {
 505                 75: mulhw({{
 506                     int64_t prod = Ra_sd * Rb_sd;
 507                     Rt = prod >> 32;
 508                 }});
 509                 11: mulhwu({{
 510                     uint64_t prod = Ra_ud * Rb_ud;
 511                     Rt = prod >> 32;
 512                 }});
 513                 235: mullw({{ int64_t prod = Ra_sd * Rb_sd; Rt = prod; }});
 514                 747: mullwo({{
 515                     int64_t src1 = Ra_sd;
 516                     int64_t src2 = Rb;
 517                     int64_t prod = src1 * src2;
 518                     Rt = prod;
 519                 }},
 520                 true);
 521
 522                 491: divw({{
 523                     int32_t src1 = Ra_sw;
 524                     int32_t src2 = Rb_sw;
 525                     if ((src1 != 0x80000000 || src2 != 0xffffffff)
 526                         && src2 != 0) {
 527                         Rt = src1 / src2;
 528                     } else {
 529                         Rt = 0;
 530                     }
 531                 }});
 532
 533                 1003: divwo({{
 534                     int32_t src1 = Ra_sw;
 535                     int32_t src2 = Rb_sw;
 536                     if ((src1 != 0x80000000 || src2 != 0xffffffff)
 537                         && src2 != 0) {
 538                         Rt = src1 / src2;
 539                     } else {
 540                         Rt = 0;
 541                         divSetOV = true;
 542                     }
 543                 }},
 544                 true);
 545
 546                 459: divwu({{
 547                     uint32_t src1 = Ra_sw;
 548                     uint32_t src2 = Rb_sw;
 549                     if (src2 != 0) {
 550                         Rt = src1 / src2;
 551                     } else {
 552                         Rt = 0;
 553                     }
 554                 }});
 555
 556                 971: divwuo({{
 557                   uint32_t src1 = Ra_sw;
 558                   uint32_t src2 = Rb_sw;
 559                   if (src2 != 0) {
 560                       Rt = src1 / src2;
 561                   } else {
 562                       Rt = 0;
 563                       divSetOV = true;
 564                   }
 565                 }},
 566                 true);
 567             }
 568
 569             default: decode XFX_XO {
 570                 format IntOp {
 571                     144: mtcrf({{
 572                         uint32_t mask = 0;
 573                         for (int i = 0; i < 8; ++i) {
 574                             if (((FXM >> i) & 0x1) == 0x1) {
 575                                 mask |= 0xf << (4 * i);
 576                             }
 577                         }
 578                         CR = (Rs & mask) | (CR & ~mask);
 579                     }});
 580
 581                     19: mfcr({{ Rt = CR; }});
 582                 }
 583             }
 584         }
 585     }
 586
 587     format LoadDispOp {
 588         48: lfs({{ Ft_sf = Mem_sf; }});
 589         50: lfd({{ Ft = Mem_df; }});
 590     }
 591
 592     format LoadDispUpdateOp {
 593         49: lfsu({{ Ft_sf = Mem_sf; }});
 594         51: lfdu({{ Ft = Mem_df; }});
 595     }
 596
 597     format StoreDispOp {
 598         52: stfs({{ Mem_sf = Fs_sf; }});
 599         54: stfd({{ Mem_df = Fs; }});
 600     }
 601
 602     format StoreDispUpdateOp {
 603         53: stfsu({{ Mem_sf = Fs_sf; }});
 604         55: stfdu({{ Mem_df = Fs; }});
 605     }
 606
 607     format FloatArithOp {
 608         59: decode A_XO {
 609             21: fadds({{ Ft = Fa + Fb; }});
 610             20: fsubs({{ Ft = Fa - Fb; }});
 611             25: fmuls({{ Ft = Fa * Fc; }});
 612             18: fdivs({{ Ft = Fa / Fb; }});
 613             29: fmadds({{ Ft = (Fa * Fc) + Fb; }});
 614             28: fmsubs({{ Ft = (Fa * Fc) - Fb; }});
 615             31: fnmadds({{ Ft = -((Fa * Fc) + Fb); }});
 616             30: fnmsubs({{ Ft = -((Fa * Fc) - Fb); }});
 617         }
 618     }
 619
 620     63: decode A_XO {
 621         format FloatArithOp {
 622             21: fadd({{ Ft = Fa + Fb; }});
 623             20: fsub({{ Ft = Fa - Fb; }});
 624             25: fmul({{ Ft = Fa * Fc; }});
 625             18: fdiv({{ Ft = Fa / Fb; }});
 626             29: fmadd({{ Ft = (Fa * Fc) + Fb; }});
 627             28: fmsub({{ Ft = (Fa * Fc) - Fb; }});
 628             31: fnmadd({{ Ft = -((Fa * Fc) + Fb); }});
 629             30: fnmsub({{ Ft = -((Fa * Fc) - Fb); }});
 630         }
 631
 632         default: decode X_XO {
 633             format FloatRCCheckOp {
 634                 72: fmr({{ Ft = Fb; }});
 635                 264: fabs({{
 636                     Ft_ud = Fb_ud;
 637                     Ft_ud = insertBits(Ft_ud, 63, 0); }});
 638                 136: fnabs({{
 639                     Ft_ud = Fb_ud;
 640                     Ft_ud = insertBits(Ft_ud, 63, 1); }});
 641                 40: fneg({{ Ft = -Fb; }});
 642                 8: fcpsgn({{
 643                     Ft_ud = Fb_ud;
 644                     Ft_ud = insertBits(Ft_ud, 63, Fa_ud<63:63>);
 645                 }});
 646             }
 647
 648             format FloatConvertOp {
 649                 12: frsp({{ Ft_sf = Fb; }});
 650                 15: fctiwz({{ Ft_sw = (int32_t)trunc(Fb); }});
 651             }
 652
 653             format FloatOp {
 654               0: fcmpu({{
 655                   uint32_t c = makeCRField(Fa, Fb);
 656                   Fpscr fpscr = FPSCR;
 657                   fpscr.fprf.fpcc = c;
 658                   FPSCR = fpscr;
 659                   CR = insertCRField(CR, BF, c);
 660               }});
 661             }
 662
 663             format FloatRCCheckOp {
 664                 583: mffs({{ Ft_ud = FPSCR; }});
 665                 134: mtfsfi({{
 666                     FPSCR = insertCRField(FPSCR, BF + (8 * (1 - W_FIELD)),
 667                                           U_FIELD);
 668                 }});
 669                 70: mtfsb0({{ FPSCR = insertBits(FPSCR, 31 - BT, 0); }});
 670                 38: mtfsb1({{ FPSCR = insertBits(FPSCR, 31 - BT, 1); }});
 671
 672                 default: decode XFL_XO {
 673                     711: mtfsf({{
 674                         if (L_FIELD == 1) { FPSCR = Fb_ud; }
 675                         else {
 676                             for (int i = 0; i < 8; ++i) {
 677                                 if (bits(FLM, i) == 1) {
 678                                     int k = 4 * (i + (8 * (1 - W_FIELD)));
 679                                     FPSCR = insertBits(FPSCR, k + 3, k,
 680                                                        bits(Fb_ud, k + 3, k));
 681                                 }
 682                             }
 683                         }
 684                     }});
 685                 }
 686             }
 687         }
 688     }
 689 }