src/arch/power/isa/decoder.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2009 The University of Edinburgh
   4 // All rights reserved.
   5 //
   6 // Redistribution and use in source and binary forms, with or without
   7 // modification, are permitted provided that the following conditions are
   8 // met: redistributions of source code must retain the above copyright
   9 // notice, this list of conditions and the following disclaimer;
  10 // redistributions in binary form must reproduce the above copyright
  11 // notice, this list of conditions and the following disclaimer in the
  12 // documentation and/or other materials provided with the distribution;
  13 // neither the name of the copyright holders nor the names of its
  14 // contributors may be used to endorse or promote products derived from
  15 // this software without specific prior written permission.
  16 //
  17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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  26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28
  29 ////////////////////////////////////////////////////////////////////
  30 //
  31 // The actual Power ISA decoder
  32 // ------------------------------
  33 //
  34 // I've used the Power ISA Book I v2.06 for instruction formats,
  35 // opcode numbers, register names, etc.
  36 //
  37 decode PO default Unknown::unknown() {
  38
  39     // Unconditionally branch to a PC-relative or absoulute address.
  40     format BranchOp {
  41         18: b({{ NIA = CIA + disp; }},
  42               {{ NIA = disp; }});
  43     }
  44
  45     // Conditionally branch to a PC-relative or absoulute address based
  46     // on CR and CTR.
  47     format BranchDispCondOp {
  48         16: bc({{ NIA = CIA + disp; }},
  49                {{ NIA = disp; }});
  50     }
  51
  52     19: decode XL_XO {
  53
  54         // Conditionally branch to an address in a register based on
  55         // either CR only or both CR and CTR.
  56         format BranchRegCondOp {
  57             16: bclr({{ NIA = LR & -4ULL; }}, true, [ IsReturn ]);
  58             528: bcctr({{ NIA = CTR & -4ULL; }});
  59             560: bctar({{ NIA = TAR & -4ULL; }}, true);
  60         }
  61
  62         // Condition register manipulation instructions.
  63         format CondLogicOp {
  64             257: crand({{
  65                 uint32_t crBa = bits(CR, 31 - ba);
  66                 uint32_t crBb = bits(CR, 31 - bb);
  67                 CR = insertBits(CR, 31 - bt, crBa & crBb);
  68             }});
  69
  70             449: cror({{
  71                 uint32_t crBa = bits(CR, 31 - ba);
  72                 uint32_t crBb = bits(CR, 31 - bb);
  73                 CR = insertBits(CR, 31 - bt, crBa | crBb);
  74             }});
  75
  76             255: crnand({{
  77                 uint32_t crBa = bits(CR, 31 - ba);
  78                 uint32_t crBb = bits(CR, 31 - bb);
  79                 CR = insertBits(CR, 31 - bt, !(crBa & crBb));
  80             }});
  81
  82             193: crxor({{
  83                 uint32_t crBa = bits(CR, 31 - ba);
  84                 uint32_t crBb = bits(CR, 31 - bb);
  85                 CR = insertBits(CR, 31 - bt, crBa ^ crBb);
  86             }});
  87
  88             33: crnor({{
  89                 uint32_t crBa = bits(CR, 31 - ba);
  90                 uint32_t crBb = bits(CR, 31 - bb);
  91                 CR = insertBits(CR, 31 - bt, !(crBa | crBb));
  92             }});
  93
  94             289: creqv({{
  95                 uint32_t crBa = bits(CR, 31 - ba);
  96                 uint32_t crBb = bits(CR, 31 - bb);
  97                 CR = insertBits(CR, 31 - bt, crBa == crBb);
  98             }});
  99
 100             129: crandc({{
 101                 uint32_t crBa = bits(CR, 31 - ba);
 102                 uint32_t crBb = bits(CR, 31 - bb);
 103                 CR = insertBits(CR, 31 - bt, crBa & !crBb);
 104             }});
 105
 106             417: crorc({{
 107                 uint32_t crBa = bits(CR, 31 - ba);
 108                 uint32_t crBb = bits(CR, 31 - bb);
 109                 CR = insertBits(CR, 31 - bt, crBa | !crBb);
 110             }});
 111         }
 112
 113         format CondMoveOp {
 114             0: mcrf({{
 115                 uint32_t crBfa = bits(CR, 31 - bfa*4, 28 - bfa*4);
 116                 CR = insertBits(CR, 31 - bf*4, 28 - bf*4, crBfa);
 117             }});
 118         }
 119
 120         format MiscOp {
 121             150: isync({{ }}, [ IsSerializeAfter ]);
 122         }
 123
 124         default: decode DX_XO {
 125             format IntDispArithOp {
 126                 2: addpcis({{ Rt = NIA + (disp << 16); }});
 127             }
 128         }
 129     }
 130
 131     17: IntOp::sc({{ return std::make_shared<SESyscallFault>(); }});
 132
 133     format LoadDispOp {
 134         34: lbz({{ Rt = Mem_ub; }});
 135         40: lhz({{ Rt = Mem_uh; }});
 136         42: lha({{ Rt = Mem_sh; }});
 137         32: lwz({{ Rt = Mem_uw; }});
 138     }
 139
 140     58: decode DS_XO {
 141         format LoadDispShiftOp {
 142             2: lwa({{ Rt = Mem_sw; }});
 143             0: ld({{ Rt = Mem; }});
 144         }
 145
 146         format LoadDispShiftUpdateOp {
 147             1: ldu({{ Rt = Mem; }});
 148         }
 149     }
 150
 151     62: decode DS_XO {
 152         format StoreDispShiftOp {
 153             0: std({{ Mem = Rs; }});
 154         }
 155
 156         format StoreDispShiftUpdateOp {
 157             1: stdu({{ Mem = Rs; }});
 158         }
 159     }
 160
 161     format LoadDispUpdateOp {
 162         35: lbzu({{ Rt = Mem_ub; }});
 163         41: lhzu({{ Rt = Mem_uh; }});
 164         43: lhau({{ Rt = Mem_sh; }});
 165         33: lwzu({{ Rt = Mem_uw; }});
 166     }
 167
 168     format StoreDispOp {
 169         38: stb({{ Mem_ub = Rs_ub; }});
 170         44: sth({{ Mem_uh = Rs_uh; }});
 171         36: stw({{ Mem_uw = Rs_uw; }});
 172     }
 173
 174     format StoreDispUpdateOp {
 175         39: stbu({{ Mem_ub = Rs_ub; }});
 176         45: sthu({{ Mem_uh = Rs_uh; }});
 177         37: stwu({{ Mem_uw = Rs_uw; }});
 178     }
 179
 180     format IntImmArithCheckRaOp {
 181         14: addi({{ Rt = Ra + simm; }},
 182                  {{ Rt = simm }});
 183         15: addis({{ Rt = Ra + (simm << 16); }},
 184                   {{ Rt = simm << 16; }});
 185     }
 186
 187     format IntImmArithOp {
 188         12: addic({{
 189             uint64_t src = Ra;
 190             Rt = src + simm;
 191         }},
 192         true);
 193
 194         13: addic_({{
 195             uint64_t src = Ra;
 196             Rt = src + simm;
 197         }},
 198         true, true);
 199
 200         8: subfic({{
 201             uint64_t src = ~Ra;
 202             Rt = src + simm + 1;
 203         }},
 204         true);
 205
 206         7: mulli({{
 207             int64_t res = Ra_sd * simm;
 208             Rt = res;
 209         }});
 210     }
 211
 212     format IntImmOp {
 213         10: cmpli({{
 214             Xer xer = XER;
 215             uint32_t cr = makeCRField(Ra, (uint32_t)uimm, xer.so);
 216             CR = insertCRField(CR, BF, cr);
 217             }});
 218         11: cmpi({{
 219             Xer xer = XER;
 220             uint32_t cr = makeCRField(Ra_sw, (int32_t)imm, xer.so);
 221             CR = insertCRField(CR, BF, cr);
 222             }});
 223     }
 224
 225     format IntImmLogicOp {
 226         24: ori({{ Ra = Rs | uimm; }});
 227         25: oris({{ Ra = Rs | (uimm << 16); }});
 228         26: xori({{ Ra = Rs ^ uimm; }});
 229         27: xoris({{ Ra = Rs ^ (uimm << 16); }});
 230         28: andi_({{ Ra = Rs & uimm; }},
 231                   true);
 232         29: andis_({{ Ra = Rs & (uimm << 16); }},
 233                    true);
 234     }
 235
 236     format IntRotateOp {
 237         21: rlwinm({{ Ra = rotateValue(Rs, sh) & fullMask; }});
 238         23: rlwnm({{ Ra = rotateValue(Rs, Rb) & fullMask; }});
 239         20: rlwimi({{ Ra = (rotateValue(Rs, sh) & fullMask) |
 240                            (Ra & ~fullMask); }});
 241     }
 242
 243     // There are a large number of instructions that have the same primary
 244     // opcode (PO) of 31. In this case, the instructions are of different
 245     // forms. For every form, the XO fields may vary in position and width.
 246     // The X, XFL, XFX and XL form instructions use bits 21 - 30 and the
 247     // XO form instructions use bits 22 - 30 as extended opcode (XO). To
 248     // avoid conflicts, instructions of each form have to be defined under
 249     // separate decode blocks. However, only a single decode block can be
 250     // associated with a particular PO and it will recognize only one type
 251     // of XO field. A solution for associating decode blocks for the other
 252     // types of XO fields with the same PO is to have the other blocks as
 253     // nested default cases.
 254     31: decode X_XO {
 255
 256         // All loads with an index register. The non-update versions
 257         // all use the value 0 if Ra == R0, not the value contained in
 258         // R0. Others update Ra with the effective address. In all cases,
 259         // Ra and Rb are source registers, Rt is the destintation.
 260         format LoadIndexOp {
 261             87: lbzx({{ Rt = Mem_ub; }});
 262             52: lbarx({{ Rt = Mem_ub; Rsv = 1; RsvLen = 1; RsvAddr = EA; }});
 263             279: lhzx({{ Rt = Mem_uh; }});
 264             343: lhax({{ Rt = Mem_sh; }});
 265             116: lharx({{ Rt = Mem_uh; Rsv = 1; RsvLen = 2; RsvAddr = EA; }});
 266             790: lhbrx({{ Rt = swap_byte(Mem_uh); }});
 267             23: lwzx({{ Rt = Mem_uw; }});
 268             341: lwax({{ Rt = Mem_sw; }});
 269             20: lwarx({{ Rt = Mem_uw; Rsv = 1; RsvLen = 4; RsvAddr = EA; }});
 270             534: lwbrx({{ Rt = swap_byte(Mem_uw); }});
 271             21: ldx({{ Rt = Mem; }});
 272             84: ldarx({{ Rt = Mem_ud; Rsv = 1; RsvLen = 8; RsvAddr = EA; }});
 273             532: ldbrx({{ Rt = swap_byte(Mem); }});
 274             535: lfsx({{ Ft_sf = Mem_sf; }});
 275             599: lfdx({{ Ft = Mem_df; }});
 276             855: lfiwax({{ Ft_uw = Mem; }});
 277         }
 278
 279         format LoadIndexUpdateOp {
 280             119: lbzux({{ Rt = Mem_ub; }});
 281             311: lhzux({{ Rt = Mem_uh; }});
 282             375: lhaux({{ Rt = Mem_sh; }});
 283             55: lwzux({{ Rt = Mem_uw; }});
 284             373: lwaux({{ Rt = Mem_sw; }});
 285             53: ldux({{ Rt = Mem; }});
 286             567: lfsux({{ Ft_sf = Mem_sf; }});
 287             631: lfdux({{ Ft = Mem_df; }});
 288         }
 289
 290         format StoreIndexOp {
 291             215: stbx({{ Mem_ub = Rs_ub; }});
 292             694: stbcx({{
 293                 bool store_performed = false;
 294                 Mem_ub = Rs_ub;
 295                 if (Rsv) {
 296                     if (RsvLen == 1) {
 297                         if (RsvAddr == EA) {
 298                             store_performed = true;
 299                         }
 300                     }
 301                 }
 302                 Xer xer = XER;
 303                 Cr cr = CR;
 304                 cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
 305                 CR = cr;
 306                 Rsv = 0;
 307             }});
 308             407: sthx({{ Mem_uh = Rs_uh; }});
 309             726: sthcx({{
 310                 bool store_performed = false;
 311                 Mem_uh = Rs_uh;
 312                 if (Rsv) {
 313                     if (RsvLen == 2) {
 314                         if (RsvAddr == EA) {
 315                             store_performed = true;
 316                         }
 317                     }
 318                 }
 319                 Xer xer = XER;
 320                 Cr cr = CR;
 321                 cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
 322                 CR = cr;
 323                 Rsv = 0;
 324             }});
 325             918: sthbrx({{ Mem_uh = swap_byte(Rs_uh); }});
 326             151: stwx({{ Mem_uw = Rs_uw; }});
 327             150: stwcx({{
 328                 bool store_performed = false;
 329                 Mem_uw = Rs_uw;
 330                 if (Rsv) {
 331                     if (RsvLen == 4) {
 332                         if (RsvAddr == EA) {
 333                             store_performed = true;
 334                         }
 335                     }
 336                 }
 337                 Xer xer = XER;
 338                 Cr cr = CR;
 339                 cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
 340                 CR = cr;
 341                 Rsv = 0;
 342             }});
 343             662: stwbrx({{ Mem_uw = swap_byte(Rs_uw); }});
 344             149: stdx({{ Mem = Rs }});
 345             214: stdcx({{
 346                 bool store_performed = false;
 347                 Mem = Rs;
 348                 if (Rsv) {
 349                     if (RsvLen == 8) {
 350                         if (RsvAddr == EA) {
 351                             store_performed = true;
 352                         }
 353                     }
 354                 }
 355                 Xer xer = XER;
 356                 Cr cr = CR;
 357                 cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
 358                 CR = cr;
 359                 Rsv = 0;
 360             }});
 361             660: stdbrx({{ Mem = swap_byte(Rs); }});
 362         }
 363
 364         format StoreIndexUpdateOp {
 365             247: stbux({{ Mem_ub = Rs_ub; }});
 366             439: sthux({{ Mem_uh = Rs_uh; }});
 367             183: stwux({{ Mem_uw = Rs_uw; }});
 368             181: stdux({{ Mem = Rs; }});
 369         }
 370
 371         format IntOp {
 372             0: cmp({{
 373                 Xer xer = XER;
 374                 uint32_t cr = makeCRField(Ra_sw, Rb_sw, xer.so);
 375                 CR = insertCRField(CR, BF, cr);
 376             }});
 377
 378             32: cmpl({{
 379                 Xer xer = XER;
 380                 uint32_t cr = makeCRField(Ra, Rb, xer.so);
 381                 CR = insertCRField(CR, BF, cr);
 382             }});
 383         }
 384
 385         // Integer logic instructions use source registers Rs and Rb,
 386         // with destination register Ra.
 387         format IntLogicOp {
 388             28: and({{ Ra = Rs & Rb; }});
 389             316: xor({{ Ra = Rs ^ Rb; }});
 390             476: nand({{ Ra = ~(Rs & Rb); }});
 391             444: or({{ Ra = Rs | Rb; }});
 392             124: nor({{ Ra = ~(Rs | Rb); }});
 393             60: andc({{ Ra = Rs & ~Rb; }});
 394             954: extsb({{ Ra = sext<8>(Rs); }});
 395             284: eqv({{ Ra = ~(Rs ^ Rb); }});
 396             412: orc({{ Ra = Rs | ~Rb; }});
 397             922: extsh({{ Ra = sext<16>(Rs); }});
 398             26: cntlzw({{ Ra = Rs == 0 ? 32 : 31 - findMsbSet(Rs); }});
 399             508: cmpb({{
 400                 uint32_t val = 0;
 401                 for (int n = 0; n < 32; n += 8) {
 402                     if(bits(Rs, n+7, n) == bits(Rb, n+7, n)) {
 403                         val = insertBits(val, n+7, n, 0xff);
 404                     }
 405                 }
 406                 Ra = val;
 407             }});
 408
 409             24: slw({{
 410                 if (Rb & 0x20) {
 411                     Ra = 0;
 412                 } else {
 413                     Ra = Rs << (Rb & 0x1f);
 414                 }
 415             }});
 416
 417             536: srw({{
 418                 if (Rb & 0x20) {
 419                     Ra = 0;
 420                 } else  {
 421                     Ra = Rs >> (Rb & 0x1f);
 422                 }
 423             }});
 424
 425             792: sraw({{
 426                 bool shiftSetCA = false;
 427                 int32_t s = Rs;
 428                 if (Rb == 0) {
 429                     Ra = Rs;
 430                     shiftSetCA = true;
 431                 } else if (Rb & 0x20) {
 432                     if (s < 0) {
 433                         Ra = (uint32_t)-1;
 434                         if (s & 0x7fffffff) {
 435                             shiftSetCA = true;
 436                         } else {
 437                             shiftSetCA = false;
 438                         }
 439                     } else {
 440                         Ra = 0;
 441                         shiftSetCA = false;
 442                     }
 443                 } else {
 444                     Ra = s >> (Rb & 0x1f);
 445                     if (s < 0 && (s << (32 - (Rb & 0x1f))) != 0) {
 446                         shiftSetCA = true;
 447                     } else {
 448                         shiftSetCA = false;
 449                     }
 450                 }
 451                 Xer xer1 = XER;
 452                 if (shiftSetCA) {
 453                     xer1.ca = 1;
 454                 } else {
 455                     xer1.ca = 0;
 456                 }
 457                 XER = xer1;
 458             }});
 459         }
 460
 461         // Integer logic instructions with a shift value.
 462         format IntShiftOp {
 463             824: srawi({{
 464                 bool shiftSetCA = false;
 465                 if (sh == 0) {
 466                     Ra = Rs;
 467                     shiftSetCA = false;
 468                 } else {
 469                     int32_t s = Rs;
 470                     Ra = s >> sh;
 471                     if (s < 0 && (s << (32 - sh)) != 0) {
 472                         shiftSetCA = true;
 473                     } else {
 474                         shiftSetCA = false;
 475                     }
 476                 }
 477                 Xer xer1 = XER;
 478                 if (shiftSetCA) {
 479                     xer1.ca = 1;
 480                 } else {
 481                     xer1.ca = 0;
 482                 }
 483                 XER = xer1;
 484             }});
 485         }
 486
 487         format StoreIndexOp {
 488             663: stfsx({{ Mem_sf = Fs_sf; }});
 489             727: stfdx({{ Mem_df = Fs; }});
 490             983: stfiwx({{ Mem = Fs_uw; }});
 491         }
 492
 493         format StoreIndexUpdateOp {
 494             695: stfsux({{ Mem_sf = Fs_sf; }});
 495             759: stfdux({{ Mem_df = Fs; }});
 496         }
 497
 498         // These instructions all provide data cache hints
 499         format MiscOp {
 500             278: dcbt({{ }});
 501             246: dcbtst({{ }});
 502             598: sync({{ }}, [ IsReadBarrier, IsWriteBarrier ]);
 503             854: eieio({{ }}, [ IsReadBarrier, IsWriteBarrier ]);
 504         }
 505
 506         // These instructions are of XO form with bit 21 as the OE bit.
 507         default: decode XO_XO {
 508
 509             // These instructions can all be reduced to the form
 510             // Rt = src1 + src2 [+ CA], therefore we just give src1 and src2
 511             // (and, if necessary, CA) definitions and let the python script
 512             // deal with setting things up correctly. We also give flags to
 513             // say which control registers to set.
 514             format IntSumOp {
 515                 266: add({{ Ra }}, {{ Rb }});
 516                 40: subf({{ ~Ra }}, {{ Rb }}, {{ 1 }});
 517                 10: addc({{ Ra }}, {{ Rb }},
 518                          computeCA = true);
 519                 8: subfc({{ ~Ra }}, {{ Rb }}, {{ 1 }},
 520                          true);
 521                 104: neg({{ ~Ra }}, {{ 1 }});
 522                 138: adde({{ Ra }}, {{ Rb }}, {{ xer.ca }},
 523                           true);
 524                 234: addme({{ Ra }}, {{ -1ULL }}, {{ xer.ca }},
 525                            true);
 526                 136: subfe({{ ~Ra }}, {{ Rb }}, {{ xer.ca }},
 527                            true);
 528                 232: subfme({{ ~Ra }}, {{ -1ULL }}, {{ xer.ca }},
 529                             true);
 530                 202: addze({{ Ra }}, {{ xer.ca }},
 531                            computeCA = true);
 532                 200: subfze({{ ~Ra }}, {{ xer.ca }},
 533                             computeCA = true);
 534             }
 535
 536             // Arithmetic instructions all use source registers Ra and Rb,
 537             // with destination register Rt.
 538             format IntArithCheckRcOp {
 539                 75: mulhw({{
 540                     uint64_t res = (int64_t)Ra_sw * Rb_sw;
 541                     res = res >> 32;
 542                     Rt = res;
 543                 }});
 544
 545                 11: mulhwu({{
 546                     uint64_t res = (uint64_t)Ra_uw * Rb_uw;
 547                     res = res >> 32;
 548                     Rt = res;
 549                 }});
 550
 551                 235: mullw({{
 552                     int64_t res = (int64_t)Ra_sw * Rb_sw;
 553                     if (res != (int32_t)res) {
 554                         setOV = true;
 555                     }
 556                     Rt = res;
 557                 }},
 558                 true);
 559
 560                 491: divw({{
 561                     int32_t src1 = Ra_sw;
 562                     int32_t src2 = Rb_sw;
 563                     if ((src1 != INT32_MIN || src2 != -1) && src2 != 0) {
 564                         Rt = (uint32_t)(src1 / src2);
 565                     } else {
 566                         Rt = 0;
 567                         setOV = true;
 568                     }
 569                 }},
 570                 true);
 571
 572                 459: divwu({{
 573                     uint32_t src1 = Ra_uw;
 574                     uint32_t src2 = Rb_uw;
 575                     if (src2 != 0) {
 576                         Rt = src1 / src2;
 577                     } else {
 578                         Rt = 0;
 579                         setOV = true;
 580                     }
 581                 }},
 582                 true);
 583             }
 584
 585             default: decode XFX_XO {
 586                 format IntOp {
 587                     339: decode SPR {
 588                         0x20: mfxer({{ Rt = XER; }});
 589                         0x100: mflr({{ Rt = LR; }});
 590                         0x120: mfctr({{ Rt = CTR; }});
 591                         0x1f9: mftar({{ Rt = TAR; }});
 592                     }
 593
 594                     467: decode SPR {
 595                         0x20: mtxer({{ XER = Rs; }});
 596                         0x100: mtlr({{ LR = Rs; }});
 597                         0x120: mtctr({{ CTR = Rs; }});
 598                         0x1f9: mttar({{ TAR = Rs; }});
 599                     }
 600
 601                     144: mtcrf({{
 602                         uint32_t mask = 0;
 603                         for (int i = 0; i < 8; ++i) {
 604                             if (((FXM >> i) & 0x1) == 0x1) {
 605                                 mask |= 0xf << (4 * i);
 606                             }
 607                         }
 608                         CR = (Rs & mask) | (CR & ~mask);
 609                     }});
 610
 611                     19: mfcr({{ Rt = CR; }});
 612
 613                     512: mcrxr({{
 614                         CR = insertCRField(CR, BF, XER<31:28>);
 615                         XER = XER<27:0>;
 616                     }});
 617                 }
 618             }
 619         }
 620     }
 621
 622     format LoadDispOp {
 623         48: lfs({{ Ft_sf = Mem_sf; }});
 624         50: lfd({{ Ft = Mem_df; }});
 625     }
 626
 627     format LoadDispUpdateOp {
 628         49: lfsu({{ Ft_sf = Mem_sf; }});
 629         51: lfdu({{ Ft = Mem_df; }});
 630     }
 631
 632     format StoreDispOp {
 633         52: stfs({{ Mem_sf = Fs_sf; }});
 634         54: stfd({{ Mem_df = Fs; }});
 635     }
 636
 637     format StoreDispUpdateOp {
 638         53: stfsu({{ Mem_sf = Fs_sf; }});
 639         55: stfdu({{ Mem_df = Fs; }});
 640     }
 641
 642     format FloatArithOp {
 643         59: decode A_XO {
 644             21: fadds({{ Ft = Fa + Fb; }});
 645             20: fsubs({{ Ft = Fa - Fb; }});
 646             25: fmuls({{ Ft = Fa * Fc; }});
 647             18: fdivs({{ Ft = Fa / Fb; }});
 648             29: fmadds({{ Ft = (Fa * Fc) + Fb; }});
 649             28: fmsubs({{ Ft = (Fa * Fc) - Fb; }});
 650             31: fnmadds({{ Ft = -((Fa * Fc) + Fb); }});
 651             30: fnmsubs({{ Ft = -((Fa * Fc) - Fb); }});
 652         }
 653     }
 654
 655     63: decode A_XO {
 656         format FloatArithOp {
 657             21: fadd({{ Ft = Fa + Fb; }});
 658             20: fsub({{ Ft = Fa - Fb; }});
 659             25: fmul({{ Ft = Fa * Fc; }});
 660             18: fdiv({{ Ft = Fa / Fb; }});
 661             29: fmadd({{ Ft = (Fa * Fc) + Fb; }});
 662             28: fmsub({{ Ft = (Fa * Fc) - Fb; }});
 663             31: fnmadd({{ Ft = -((Fa * Fc) + Fb); }});
 664             30: fnmsub({{ Ft = -((Fa * Fc) - Fb); }});
 665         }
 666
 667         default: decode X_XO {
 668             format FloatRCCheckOp {
 669                 72: fmr({{ Ft = Fb; }});
 670                 264: fabs({{
 671                     Ft_ud = Fb_ud;
 672                     Ft_ud = insertBits(Ft_ud, 63, 0); }});
 673                 136: fnabs({{
 674                     Ft_ud = Fb_ud;
 675                     Ft_ud = insertBits(Ft_ud, 63, 1); }});
 676                 40: fneg({{ Ft = -Fb; }});
 677                 8: fcpsgn({{
 678                     Ft_ud = Fb_ud;
 679                     Ft_ud = insertBits(Ft_ud, 63, Fa_ud<63:63>);
 680                 }});
 681             }
 682
 683             format FloatConvertOp {
 684                 12: frsp({{ Ft_sf = Fb; }});
 685                 15: fctiwz({{ Ft_sw = (int32_t)trunc(Fb); }});
 686             }
 687
 688             format FloatOp {
 689               0: fcmpu({{
 690                   uint32_t c = makeCRField(Fa, Fb);
 691                   Fpscr fpscr = FPSCR;
 692                   fpscr.fprf.fpcc = c;
 693                   FPSCR = fpscr;
 694                   CR = insertCRField(CR, BF, c);
 695               }});
 696             }
 697
 698             format FloatRCCheckOp {
 699                 583: mffs({{ Ft_ud = FPSCR; }});
 700                 134: mtfsfi({{
 701                     FPSCR = insertCRField(FPSCR, BF + (8 * (1 - W_FIELD)),
 702                                           U_FIELD);
 703                 }});
 704                 70: mtfsb0({{ FPSCR = insertBits(FPSCR, 31 - BT, 0); }});
 705                 38: mtfsb1({{ FPSCR = insertBits(FPSCR, 31 - BT, 1); }});
 706
 707                 default: decode XFL_XO {
 708                     711: mtfsf({{
 709                         if (L_FIELD == 1) { FPSCR = Fb_ud; }
 710                         else {
 711                             for (int i = 0; i < 8; ++i) {
 712                                 if (bits(FLM, i) == 1) {
 713                                     int k = 4 * (i + (8 * (1 - W_FIELD)));
 714                                     FPSCR = insertBits(FPSCR, k + 3, k,
 715                                                        bits(Fb_ud, k + 3, k));
 716                                 }
 717                             }
 718                         }
 719                     }});
 720                 }
 721             }
 722         }
 723     }
 724 }