src/arch/power/isa/decoder.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2009 The University of Edinburgh
   4 // All rights reserved.
   5 //
   6 // Redistribution and use in source and binary forms, with or without
   7 // modification, are permitted provided that the following conditions are
   8 // met: redistributions of source code must retain the above copyright
   9 // notice, this list of conditions and the following disclaimer;
  10 // redistributions in binary form must reproduce the above copyright
  11 // notice, this list of conditions and the following disclaimer in the
  12 // documentation and/or other materials provided with the distribution;
  13 // neither the name of the copyright holders nor the names of its
  14 // contributors may be used to endorse or promote products derived from
  15 // this software without specific prior written permission.
  16 //
  17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28 //
  29 // Authors: Timothy M. Jones
  30
  31 ////////////////////////////////////////////////////////////////////
  32 //
  33 // The actual Power ISA decoder
  34 // ------------------------------
  35 //
  36 // I've used the Power ISA Book I v2.06 for instruction formats,
  37 // opcode numbers, register names, etc.
  38 //
  39 decode OPCODE default Unknown::unknown() {
  40
  41     format IntImmOp {
  42         10: cmpli({{
  43             Xer xer = XER;
  44             uint32_t cr = makeCRField(Ra, (uint32_t)uimm, xer.so);
  45             CR = insertCRField(CR, BF, cr);
  46             }});
  47         11: cmpi({{
  48             Xer xer = XER;
  49             uint32_t cr = makeCRField(Ra_sw, (int32_t)imm, xer.so);
  50             CR = insertCRField(CR, BF, cr);
  51             }});
  52     }
  53
  54     // Some instructions use bits 21 - 30, others 22 - 30. We have to use
  55     // the larger size to account for all opcodes. For those that use the
  56     // smaller value, the OE bit is bit 21. Therefore, we have two versions
  57     // of each instruction: 1 with OE set, the other without. For an
  58     // example see 'add' and 'addo'.
  59     31: decode XO_XO {
  60
  61         // These instructions can all be reduced to the form
  62         // Rt = src1 + src2 [+ CA], therefore we just give src1 and src2
  63         // (and, if necessary, CA) definitions and let the python script
  64         // deal with setting things up correctly. We also give flags to
  65         // say which control registers to set.
  66         format IntSumOp {
  67             266: add({{ Ra }}, {{ Rb }});
  68             40: subf({{ ~Ra }}, {{ Rb }}, {{ 1 }});
  69             10: addc({{ Ra }}, {{ Rb }},
  70                      computeCA = true);
  71             8: subfc({{ ~Ra }}, {{ Rb }}, {{ 1 }},
  72                      true);
  73             104: neg({{ ~Ra }}, {{ 1 }});
  74             138: adde({{ Ra }}, {{ Rb }}, {{ xer.ca }},
  75                       true);
  76             234: addme({{ Ra }}, {{ (uint32_t)-1 }}, {{ xer.ca }},
  77                        true);
  78             136: subfe({{ ~Ra }}, {{ Rb }}, {{ xer.ca }},
  79                        true);
  80             232: subfme({{ ~Ra }}, {{ (uint32_t)-1 }}, {{ xer.ca }},
  81                         true);
  82             202: addze({{ Ra }}, {{ xer.ca }},
  83                        computeCA = true);
  84             200: subfze({{ ~Ra }}, {{ xer.ca }},
  85                         computeCA = true);
  86         }
  87
  88         // Arithmetic instructions all use source registers Ra and Rb,
  89         // with destination register Rt.
  90         format IntArithOp {
  91             75: mulhw({{ int64_t prod = Ra_sd * Rb_sd; Rt = prod >> 32; }});
  92             11: mulhwu({{ uint64_t prod = Ra_ud * Rb_ud; Rt = prod >> 32; }});
  93             235: mullw({{ int64_t prod = Ra_sd * Rb_sd; Rt = prod; }});
  94             747: mullwo({{
  95                 int64_t src1 = Ra_sd;
  96                 int64_t src2 = Rb;
  97                 int64_t prod = src1 * src2;
  98                 Rt = prod;
  99             }},
 100             true);
 101
 102             491: divw({{
 103                 int32_t src1 = Ra_sw;
 104                 int32_t src2 = Rb_sw;
 105                 if ((src1 != 0x80000000 || src2 != 0xffffffff)
 106                     && src2 != 0) {
 107                     Rt = src1 / src2;
 108                 } else {
 109                     Rt = 0;
 110                 }
 111             }});
 112
 113             1003: divwo({{
 114                 int32_t src1 = Ra_sw;
 115                 int32_t src2 = Rb_sw;
 116                 if ((src1 != 0x80000000 || src2 != 0xffffffff)
 117                     && src2 != 0) {
 118                     Rt = src1 / src2;
 119                 } else {
 120                     Rt = 0;
 121                     divSetOV = true;
 122                 }
 123             }},
 124             true);
 125
 126             459: divwu({{
 127                 uint32_t src1 = Ra_sw;
 128                 uint32_t src2 = Rb_sw;
 129                 if (src2 != 0) {
 130                     Rt = src1 / src2;
 131                 } else {
 132                     Rt = 0;
 133                 }
 134             }});
 135
 136             971: divwuo({{
 137               uint32_t src1 = Ra_sw;
 138               uint32_t src2 = Rb_sw;
 139               if (src2 != 0) {
 140                   Rt = src1 / src2;
 141               } else {
 142                   Rt = 0;
 143                   divSetOV = true;
 144               }
 145             }},
 146             true);
 147         }
 148
 149         // Integer logic instructions use source registers Rs and Rb,
 150         // with destination register Ra.
 151         format IntLogicOp {
 152             28: and({{ Ra = Rs & Rb; }});
 153             316: xor({{ Ra = Rs ^ Rb; }});
 154             476: nand({{ Ra = ~(Rs & Rb); }});
 155             444: or({{ Ra = Rs | Rb; }});
 156             124: nor({{ Ra = ~(Rs | Rb); }});
 157             60: andc({{ Ra = Rs & ~Rb; }});
 158             954: extsb({{ Ra = sext<8>(Rs); }});
 159             284: eqv({{ Ra = ~(Rs ^ Rb); }});
 160             412: orc({{ Ra = Rs | ~Rb; }});
 161             922: extsh({{ Ra = sext<16>(Rs); }});
 162             26: cntlzw({{ Ra = Rs == 0 ? 32 : 31 - findMsbSet(Rs); }});
 163             508: cmpb({{
 164                 uint32_t val = 0;
 165                 for (int n = 0; n < 32; n += 8) {
 166                     if(bits(Rs, n+7, n) == bits(Rb, n+7, n)) {
 167                         val = insertBits(val, n+7, n, 0xff);
 168                     }
 169                 }
 170                 Ra = val;
 171             }});
 172
 173             24: slw({{
 174                 if (Rb & 0x20) {
 175                     Ra = 0;
 176                 } else {
 177                     Ra = Rs << (Rb & 0x1f);
 178                 }
 179             }});
 180
 181             536: srw({{
 182                 if (Rb & 0x20) {
 183                     Ra = 0;
 184                 } else  {
 185                     Ra = Rs >> (Rb & 0x1f);
 186                 }
 187             }});
 188
 189             792: sraw({{
 190                 bool shiftSetCA = false;
 191                 int32_t s = Rs;
 192                 if (Rb == 0) {
 193                     Ra = Rs;
 194                     shiftSetCA = true;
 195                 } else if (Rb & 0x20) {
 196                     if (s < 0) {
 197                         Ra = (uint32_t)-1;
 198                         if (s & 0x7fffffff) {
 199                             shiftSetCA = true;
 200                         } else {
 201                             shiftSetCA = false;
 202                         }
 203                     } else {
 204                         Ra = 0;
 205                         shiftSetCA = false;
 206                     }
 207                 } else {
 208                     Ra = s >> (Rb & 0x1f);
 209                     if (s < 0 && (s << (32 - (Rb & 0x1f))) != 0) {
 210                         shiftSetCA = true;
 211                     } else {
 212                         shiftSetCA = false;
 213                     }
 214                 }
 215                 Xer xer1 = XER;
 216                 if (shiftSetCA) {
 217                     xer1.ca = 1;
 218                 } else {
 219                     xer1.ca = 0;
 220                 }
 221                 XER = xer1;
 222             }});
 223         }
 224
 225         // Integer logic instructions with a shift value.
 226         format IntShiftOp {
 227             824: srawi({{
 228                 bool shiftSetCA = false;
 229                 if (sh == 0) {
 230                     Ra = Rs;
 231                     shiftSetCA = false;
 232                 } else {
 233                     int32_t s = Rs;
 234                     Ra = s >> sh;
 235                     if (s < 0 && (s << (32 - sh)) != 0) {
 236                         shiftSetCA = true;
 237                     } else {
 238                         shiftSetCA = false;
 239                     }
 240                 }
 241                 Xer xer1 = XER;
 242                 if (shiftSetCA) {
 243                     xer1.ca = 1;
 244                 } else {
 245                     xer1.ca = 0;
 246                 }
 247                 XER = xer1;
 248             }});
 249         }
 250
 251         // Generic integer format instructions.
 252         format IntOp {
 253             0: cmp({{
 254                 Xer xer = XER;
 255                 uint32_t cr = makeCRField(Ra_sw, Rb_sw, xer.so);
 256                 CR = insertCRField(CR, BF, cr);
 257                 }});
 258             32: cmpl({{
 259                 Xer xer = XER;
 260                 uint32_t cr = makeCRField(Ra, Rb, xer.so);
 261                 CR = insertCRField(CR, BF, cr);
 262                 }});
 263             144: mtcrf({{
 264                 uint32_t mask = 0;
 265                 for (int i = 0; i < 8; ++i) {
 266                     if (((FXM >> i) & 0x1) == 0x1) {
 267                         mask |= 0xf << (4 * i);
 268                     }
 269                 }
 270                 CR = (Rs & mask) | (CR & ~mask);
 271                 }});
 272             19: mfcr({{ Rt = CR; }});
 273             339: decode SPR {
 274                 0x20: mfxer({{ Rt = XER; }});
 275                 0x100: mflr({{ Rt = LR; }});
 276                 0x120: mfctr({{ Rt = CTR; }});
 277             }
 278             467: decode SPR {
 279                 0x20: mtxer({{ XER = Rs; }});
 280                 0x100: mtlr({{ LR = Rs; }});
 281                 0x120: mtctr({{ CTR = Rs; }});
 282             }
 283         }
 284
 285         // All loads with an index register. The non-update versions
 286         // all use the value 0 if Ra == R0, not the value contained in
 287         // R0. Others update Ra with the effective address. In all cases,
 288         // Ra and Rb are source registers, Rt is the destintation.
 289         format LoadIndexOp {
 290             87: lbzx({{ Rt = Mem_ub; }});
 291             279: lhzx({{ Rt = Mem_uh; }});
 292             343: lhax({{ Rt = Mem_sh; }});
 293             23: lwzx({{ Rt = Mem; }});
 294             341: lwax({{ Rt = Mem_sw; }});
 295             20: lwarx({{ Rt = Mem_sw; Rsv = 1; RsvLen = 4; RsvAddr = EA; }});
 296             535: lfsx({{ Ft_sf = Mem_sf; }});
 297             599: lfdx({{ Ft = Mem_df; }});
 298             855: lfiwax({{ Ft_uw = Mem; }});
 299         }
 300
 301         format LoadIndexUpdateOp {
 302             119: lbzux({{ Rt = Mem_ub; }});
 303             311: lhzux({{ Rt = Mem_uh; }});
 304             375: lhaux({{ Rt = Mem_sh; }});
 305             55: lwzux({{ Rt = Mem; }});
 306             373: lwaux({{ Rt = Mem_sw; }});
 307             567: lfsux({{ Ft_sf = Mem_sf; }});
 308             631: lfdux({{ Ft = Mem_df; }});
 309         }
 310
 311         format StoreIndexOp {
 312             215: stbx({{ Mem_ub = Rs_ub; }});
 313             407: sthx({{ Mem_uh = Rs_uh; }});
 314             151: stwx({{ Mem = Rs; }});
 315             150: stwcx({{
 316                 bool store_performed = false;
 317                 Mem = Rs;
 318                 if (Rsv) {
 319                     if (RsvLen == 4) {
 320                         if (RsvAddr == EA) {
 321                             store_performed = true;
 322                         }
 323                     }
 324                 }
 325                 Xer xer = XER;
 326                 Cr cr = CR;
 327                 cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
 328                 CR = cr;
 329                 Rsv = 0;
 330             }});
 331             663: stfsx({{ Mem_sf = Fs_sf; }});
 332             727: stfdx({{ Mem_df = Fs; }});
 333             983: stfiwx({{ Mem = Fs_uw; }});
 334         }
 335
 336         format StoreIndexUpdateOp {
 337             247: stbux({{ Mem_ub = Rs_ub; }});
 338             439: sthux({{ Mem_uh = Rs_uh; }});
 339             183: stwux({{ Mem = Rs; }});
 340             695: stfsux({{ Mem_sf = Fs_sf; }});
 341             759: stfdux({{ Mem_df = Fs; }});
 342         }
 343
 344         // These instructions all provide data cache hints
 345         format MiscOp {
 346             278: dcbt({{ }});
 347             246: dcbtst({{ }});
 348             598: sync({{ }}, [ IsMemBarrier ]);
 349             854: eieio({{ }}, [ IsMemBarrier ]);
 350         }
 351     }
 352
 353     format IntImmArithCheckRaOp {
 354         14: addi({{ Rt = Ra + imm; }},
 355                  {{ Rt = imm }});
 356         15: addis({{ Rt = Ra + (imm << 16); }},
 357                   {{ Rt = imm << 16; }});
 358     }
 359
 360     format IntImmArithOp {
 361         12: addic({{ uint32_t src = Ra; Rt = src + imm; }},
 362                   [computeCA]);
 363         13: addic_({{ uint32_t src = Ra; Rt = src + imm; }},
 364                    [computeCA, computeCR0]);
 365         8: subfic({{ int32_t src = ~Ra; Rt = src + imm + 1; }},
 366                   [computeCA]);
 367         7: mulli({{
 368             int32_t src = Ra_sw;
 369             int64_t prod = src * imm;
 370             Rt = (uint32_t)prod;
 371         }});
 372     }
 373
 374     format IntImmLogicOp {
 375         24: ori({{ Ra = Rs | uimm; }});
 376         25: oris({{ Ra = Rs | (uimm << 16); }});
 377         26: xori({{ Ra = Rs ^ uimm; }});
 378         27: xoris({{ Ra = Rs ^ (uimm << 16); }});
 379         28: andi_({{ Ra = Rs & uimm; }},
 380                   true);
 381         29: andis_({{ Ra = Rs & (uimm << 16); }},
 382                    true);
 383     }
 384
 385     16: decode AA {
 386
 387         // Conditionally branch relative to PC based on CR and CTR.
 388         format BranchPCRelCondCtr {
 389             0: bc({{ NPC = (uint32_t)(PC + disp); }});
 390         }
 391
 392         // Conditionally branch to fixed address based on CR and CTR.
 393         format BranchNonPCRelCondCtr {
 394             1: bca({{ NPC = targetAddr; }});
 395         }
 396     }
 397
 398     18: decode AA {
 399
 400         // Unconditionally branch relative to PC.
 401         format BranchPCRel {
 402             0: b({{ NPC = (uint32_t)(PC + disp); }});
 403         }
 404
 405         // Unconditionally branch to fixed address.
 406         format BranchNonPCRel {
 407             1: ba({{ NPC = targetAddr; }});
 408         }
 409     }
 410
 411     19: decode XO_XO {
 412
 413         // Conditionally branch to address in LR based on CR and CTR.
 414         format BranchLrCondCtr {
 415            16: bclr({{ NPC = LR & 0xfffffffc; }});
 416         }
 417
 418         // Conditionally branch to address in CTR based on CR.
 419         format BranchCtrCond {
 420            528: bcctr({{ NPC = CTR & 0xfffffffc; }});
 421         }
 422
 423         // Condition register manipulation instructions.
 424         format CondLogicOp {
 425             257: crand({{
 426                 uint32_t crBa = bits(CR, 31 - ba);
 427                 uint32_t crBb = bits(CR, 31 - bb);
 428                 CR = insertBits(CR, 31 - bt, crBa & crBb);
 429             }});
 430             449: cror({{
 431                 uint32_t crBa = bits(CR, 31 - ba);
 432                 uint32_t crBb = bits(CR, 31 - bb);
 433                 CR = insertBits(CR, 31 - bt, crBa | crBb);
 434             }});
 435             255: crnand({{
 436                 uint32_t crBa = bits(CR, 31 - ba);
 437                 uint32_t crBb = bits(CR, 31 - bb);
 438                 CR = insertBits(CR, 31 - bt, !(crBa & crBb));
 439             }});
 440             193: crxor({{
 441                 uint32_t crBa = bits(CR, 31 - ba);
 442                 uint32_t crBb = bits(CR, 31 - bb);
 443                 CR = insertBits(CR, 31 - bt, crBa ^ crBb);
 444             }});
 445             33: crnor({{
 446                 uint32_t crBa = bits(CR, 31 - ba);
 447                 uint32_t crBb = bits(CR, 31 - bb);
 448                 CR = insertBits(CR, 31 - bt, !(crBa | crBb));
 449             }});
 450             289: creqv({{
 451                 uint32_t crBa = bits(CR, 31 - ba);
 452                 uint32_t crBb = bits(CR, 31 - bb);
 453                 CR = insertBits(CR, 31 - bt, crBa == crBb);
 454             }});
 455             129: crandc({{
 456                 uint32_t crBa = bits(CR, 31 - ba);
 457                 uint32_t crBb = bits(CR, 31 - bb);
 458                 CR = insertBits(CR, 31 - bt, crBa & !crBb);
 459             }});
 460             417: crorc({{
 461                 uint32_t crBa = bits(CR, 31 - ba);
 462                 uint32_t crBb = bits(CR, 31 - bb);
 463                 CR = insertBits(CR, 31 - bt, crBa | !crBb);
 464             }});
 465         }
 466         format CondMoveOp {
 467             0: mcrf({{
 468                 uint32_t crBfa = bits(CR, 31 - bfa*4, 28 - bfa*4);
 469                 CR = insertBits(CR, 31 - bf*4, 28 - bf*4, crBfa);
 470             }});
 471         }
 472         format MiscOp {
 473             150: isync({{ }}, [ IsSerializeAfter ]);
 474         }
 475     }
 476
 477     format IntRotateOp {
 478         21: rlwinm({{ Ra = rotateValue(Rs, sh) & fullMask; }});
 479         23: rlwnm({{ Ra = rotateValue(Rs, Rb) & fullMask; }});
 480         20: rlwimi({{ Ra = (rotateValue(Rs, sh) & fullMask) | (Ra & ~fullMask); }});
 481     }
 482
 483     format LoadDispOp {
 484         34: lbz({{ Rt = Mem_ub; }});
 485         40: lhz({{ Rt = Mem_uh; }});
 486         42: lha({{ Rt = Mem_sh; }});
 487         32: lwz({{ Rt = Mem; }});
 488         58: lwa({{ Rt = Mem_sw; }},
 489                 {{ EA = Ra + (disp & 0xfffffffc); }},
 490                 {{ EA = disp & 0xfffffffc; }});
 491         48: lfs({{ Ft_sf = Mem_sf; }});
 492         50: lfd({{ Ft = Mem_df; }});
 493     }
 494
 495     format LoadDispUpdateOp {
 496         35: lbzu({{ Rt = Mem_ub; }});
 497         41: lhzu({{ Rt = Mem_uh; }});
 498         43: lhau({{ Rt = Mem_sh; }});
 499         33: lwzu({{ Rt = Mem; }});
 500         49: lfsu({{ Ft_sf = Mem_sf; }});
 501         51: lfdu({{ Ft = Mem_df; }});
 502     }
 503
 504     format StoreDispOp {
 505         38: stb({{ Mem_ub = Rs_ub; }});
 506         44: sth({{ Mem_uh = Rs_uh; }});
 507         36: stw({{ Mem = Rs; }});
 508         52: stfs({{ Mem_sf = Fs_sf; }});
 509         54: stfd({{ Mem_df = Fs; }});
 510     }
 511
 512     format StoreDispUpdateOp {
 513         39: stbu({{ Mem_ub = Rs_ub; }});
 514         45: sthu({{ Mem_uh = Rs_uh; }});
 515         37: stwu({{ Mem = Rs; }});
 516         53: stfsu({{ Mem_sf = Fs_sf; }});
 517         55: stfdu({{ Mem_df = Fs; }});
 518     }
 519
 520     17: IntOp::sc({{ xc->syscall(R0, &fault); }},
 521                   [ IsSyscall, IsNonSpeculative, IsSerializeAfter ]);
 522
 523     format FloatArithOp {
 524         59: decode A_XO {
 525             21: fadds({{ Ft = Fa + Fb; }});
 526             20: fsubs({{ Ft = Fa - Fb; }});
 527             25: fmuls({{ Ft = Fa * Fc; }});
 528             18: fdivs({{ Ft = Fa / Fb; }});
 529             29: fmadds({{ Ft = (Fa * Fc) + Fb; }});
 530             28: fmsubs({{ Ft = (Fa * Fc) - Fb; }});
 531             31: fnmadds({{ Ft = -((Fa * Fc) + Fb); }});
 532             30: fnmsubs({{ Ft = -((Fa * Fc) - Fb); }});
 533         }
 534     }
 535
 536     63: decode A_XO {
 537         format FloatArithOp {
 538             21: fadd({{ Ft = Fa + Fb; }});
 539             20: fsub({{ Ft = Fa - Fb; }});
 540             25: fmul({{ Ft = Fa * Fc; }});
 541             18: fdiv({{ Ft = Fa / Fb; }});
 542             29: fmadd({{ Ft = (Fa * Fc) + Fb; }});
 543             28: fmsub({{ Ft = (Fa * Fc) - Fb; }});
 544             31: fnmadd({{ Ft = -((Fa * Fc) + Fb); }});
 545             30: fnmsub({{ Ft = -((Fa * Fc) - Fb); }});
 546         }
 547
 548         default: decode XO_XO {
 549             format FloatConvertOp {
 550                 12: frsp({{ Ft_sf = Fb; }});
 551                 15: fctiwz({{ Ft_sw = (int32_t)trunc(Fb); }});
 552             }
 553
 554             format FloatOp {
 555               0: fcmpu({{
 556                   uint32_t c = makeCRField(Fa, Fb);
 557                   Fpscr fpscr = FPSCR;
 558                   fpscr.fprf.fpcc = c;
 559                   FPSCR = fpscr;
 560                   CR = insertCRField(CR, BF, c);
 561               }});
 562             }
 563
 564             format FloatRCCheckOp {
 565                 72: fmr({{ Ft = Fb; }});
 566                 264: fabs({{
 567                     Ft_ud = Fb_ud;
 568                     Ft_ud = insertBits(Ft_ud, 63, 0); }});
 569                 136: fnabs({{
 570                     Ft_ud = Fb_ud;
 571                     Ft_ud = insertBits(Ft_ud, 63, 1); }});
 572                 40: fneg({{ Ft = -Fb; }});
 573                 8: fcpsgn({{
 574                     Ft_ud = Fb_ud;
 575                     Ft_ud = insertBits(Ft_ud, 63, Fa_ud<63:63>);
 576                 }});
 577                 583: mffs({{ Ft_ud = FPSCR; }});
 578                 134: mtfsfi({{
 579                     FPSCR = insertCRField(FPSCR, BF + (8 * (1 - W_FIELD)),
 580                                           U_FIELD);
 581                 }});
 582                 711: mtfsf({{
 583                     if (L_FIELD == 1) { FPSCR = Fb_ud; }
 584                     else {
 585                         for (int i = 0; i < 8; ++i) {
 586                             if (bits(FLM, i) == 1) {
 587                                 int k = 4 * (i + (8 * (1 - W_FIELD)));
 588                                 FPSCR = insertBits(FPSCR, k + 3, k,
 589                                                    bits(Fb_ud, k + 3, k));
 590                             }
 591                         }
 592                     }
 593                 }});
 594                 70: mtfsb0({{ FPSCR = insertBits(FPSCR, 31 - BT, 0); }});
 595                 38: mtfsb1({{ FPSCR = insertBits(FPSCR, 31 - BT, 1); }});
 596             }
 597         }
 598     }
 599 }