src/arch/power/isa/decoder.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2009 The University of Edinburgh
   4 // All rights reserved.
   5 //
   6 // Redistribution and use in source and binary forms, with or without
   7 // modification, are permitted provided that the following conditions are
   8 // met: redistributions of source code must retain the above copyright
   9 // notice, this list of conditions and the following disclaimer;
  10 // redistributions in binary form must reproduce the above copyright
  11 // notice, this list of conditions and the following disclaimer in the
  12 // documentation and/or other materials provided with the distribution;
  13 // neither the name of the copyright holders nor the names of its
  14 // contributors may be used to endorse or promote products derived from
  15 // this software without specific prior written permission.
  16 //
  17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28
  29 ////////////////////////////////////////////////////////////////////
  30 //
  31 // The actual Power ISA decoder
  32 // ------------------------------
  33 //
  34 // I've used the Power ISA Book I v2.06 for instruction formats,
  35 // opcode numbers, register names, etc.
  36 //
  37 decode PO default Unknown::unknown() {
  38
  39     18: decode AA {
  40
  41         // Unconditionally branch relative to PC.
  42         format BranchPCRel {
  43             0: b({{ NIA = (uint32_t)(CIA + disp); }});
  44         }
  45
  46         // Unconditionally branch to fixed address.
  47         format BranchNonPCRel {
  48             1: ba({{ NIA = targetAddr; }});
  49         }
  50     }
  51
  52     16: decode AA {
  53
  54         // Conditionally branch relative to PC based on CR and CTR.
  55         format BranchPCRelCondCtr {
  56             0: bc({{ NIA = (uint32_t)(CIA + disp); }});
  57         }
  58
  59         // Conditionally branch to fixed address based on CR and CTR.
  60         format BranchNonPCRelCondCtr {
  61             1: bca({{ NIA = targetAddr; }});
  62         }
  63     }
  64
  65     19: decode XL_XO {
  66
  67         // Conditionally branch to address in LR based on CR and CTR.
  68         format BranchLrCondCtr {
  69            16: bclr({{ NIA = LR & 0xfffffffc; }});
  70         }
  71
  72         // Conditionally branch to address in CTR based on CR.
  73         format BranchCtrCond {
  74            528: bcctr({{ NIA = CTR & 0xfffffffc; }});
  75         }
  76
  77         // Condition register manipulation instructions.
  78         format CondLogicOp {
  79             257: crand({{
  80                 uint32_t crBa = bits(CR, 31 - ba);
  81                 uint32_t crBb = bits(CR, 31 - bb);
  82                 CR = insertBits(CR, 31 - bt, crBa & crBb);
  83             }});
  84
  85             449: cror({{
  86                 uint32_t crBa = bits(CR, 31 - ba);
  87                 uint32_t crBb = bits(CR, 31 - bb);
  88                 CR = insertBits(CR, 31 - bt, crBa | crBb);
  89             }});
  90
  91             255: crnand({{
  92                 uint32_t crBa = bits(CR, 31 - ba);
  93                 uint32_t crBb = bits(CR, 31 - bb);
  94                 CR = insertBits(CR, 31 - bt, !(crBa & crBb));
  95             }});
  96
  97             193: crxor({{
  98                 uint32_t crBa = bits(CR, 31 - ba);
  99                 uint32_t crBb = bits(CR, 31 - bb);
 100                 CR = insertBits(CR, 31 - bt, crBa ^ crBb);
 101             }});
 102
 103             33: crnor({{
 104                 uint32_t crBa = bits(CR, 31 - ba);
 105                 uint32_t crBb = bits(CR, 31 - bb);
 106                 CR = insertBits(CR, 31 - bt, !(crBa | crBb));
 107             }});
 108
 109             289: creqv({{
 110                 uint32_t crBa = bits(CR, 31 - ba);
 111                 uint32_t crBb = bits(CR, 31 - bb);
 112                 CR = insertBits(CR, 31 - bt, crBa == crBb);
 113             }});
 114
 115             129: crandc({{
 116                 uint32_t crBa = bits(CR, 31 - ba);
 117                 uint32_t crBb = bits(CR, 31 - bb);
 118                 CR = insertBits(CR, 31 - bt, crBa & !crBb);
 119             }});
 120
 121             417: crorc({{
 122                 uint32_t crBa = bits(CR, 31 - ba);
 123                 uint32_t crBb = bits(CR, 31 - bb);
 124                 CR = insertBits(CR, 31 - bt, crBa | !crBb);
 125             }});
 126         }
 127
 128         format CondMoveOp {
 129             0: mcrf({{
 130                 uint32_t crBfa = bits(CR, 31 - bfa*4, 28 - bfa*4);
 131                 CR = insertBits(CR, 31 - bf*4, 28 - bf*4, crBfa);
 132             }});
 133         }
 134
 135         format MiscOp {
 136             150: isync({{ }}, [ IsSerializeAfter ]);
 137         }
 138     }
 139
 140     17: IntOp::sc({{ xc->syscall(R0, &fault); }},
 141                   [ IsSyscall, IsNonSpeculative, IsSerializeAfter ]);
 142
 143     format LoadDispOp {
 144         34: lbz({{ Rt = Mem_ub; }});
 145         40: lhz({{ Rt = Mem_uh; }});
 146         42: lha({{ Rt = Mem_sh; }});
 147         32: lwz({{ Rt = Mem_uw; }});
 148     }
 149
 150     58: decode DS_XO {
 151         format LoadDispShiftOp {
 152             2: lwa({{ Rt = Mem_sw; }});
 153             0: ld({{ Rt = Mem; }});
 154         }
 155
 156         format LoadDispShiftUpdateOp {
 157             1: ldu({{ Rt = Mem; }});
 158         }
 159     }
 160
 161     62: decode DS_XO {
 162         format StoreDispShiftOp {
 163             0: std({{ Mem = Rs; }});
 164         }
 165
 166         format StoreDispShiftUpdateOp {
 167             1: stdu({{ Mem = Rs; }});
 168         }
 169     }
 170
 171     format LoadDispUpdateOp {
 172         35: lbzu({{ Rt = Mem_ub; }});
 173         41: lhzu({{ Rt = Mem_uh; }});
 174         43: lhau({{ Rt = Mem_sh; }});
 175         33: lwzu({{ Rt = Mem_uw; }});
 176     }
 177
 178     format StoreDispOp {
 179         38: stb({{ Mem_ub = Rs_ub; }});
 180         44: sth({{ Mem_uh = Rs_uh; }});
 181         36: stw({{ Mem = Rs_uw; }});
 182     }
 183
 184     format StoreDispUpdateOp {
 185         39: stbu({{ Mem_ub = Rs_ub; }});
 186         45: sthu({{ Mem_uh = Rs_uh; }});
 187         37: stwu({{ Mem = Rs_uw; }});
 188     }
 189
 190     format IntImmArithCheckRaOp {
 191         14: addi({{ Rt = Ra + simm; }},
 192                  {{ Rt = simm }});
 193         15: addis({{ Rt = Ra + (simm << 16); }},
 194                   {{ Rt = simm << 16; }});
 195     }
 196
 197     format IntImmArithOp {
 198         12: addic({{
 199             uint64_t src = Ra;
 200             Rt = src + simm;
 201         }},
 202         true);
 203
 204         13: addic_({{
 205             uint64_t src = Ra;
 206             Rt = src + simm;
 207         }},
 208         true, true);
 209
 210         8: subfic({{
 211             uint64_t src = ~Ra;
 212             Rt = src + simm + 1;
 213         }},
 214         true);
 215
 216         7: mulli({{
 217             int32_t src = Ra_sw;
 218             int64_t prod = src * simm;
 219             Rt = (uint32_t)prod;
 220         }});
 221     }
 222
 223     format IntImmOp {
 224         10: cmpli({{
 225             Xer xer = XER;
 226             uint32_t cr = makeCRField(Ra, (uint32_t)uimm, xer.so);
 227             CR = insertCRField(CR, BF, cr);
 228             }});
 229         11: cmpi({{
 230             Xer xer = XER;
 231             uint32_t cr = makeCRField(Ra_sw, (int32_t)imm, xer.so);
 232             CR = insertCRField(CR, BF, cr);
 233             }});
 234     }
 235
 236     format IntImmLogicOp {
 237         24: ori({{ Ra = Rs | uimm; }});
 238         25: oris({{ Ra = Rs | (uimm << 16); }});
 239         26: xori({{ Ra = Rs ^ uimm; }});
 240         27: xoris({{ Ra = Rs ^ (uimm << 16); }});
 241         28: andi_({{ Ra = Rs & uimm; }},
 242                   true);
 243         29: andis_({{ Ra = Rs & (uimm << 16); }},
 244                    true);
 245     }
 246
 247     format IntRotateOp {
 248         21: rlwinm({{ Ra = rotateValue(Rs, sh) & fullMask; }});
 249         23: rlwnm({{ Ra = rotateValue(Rs, Rb) & fullMask; }});
 250         20: rlwimi({{ Ra = (rotateValue(Rs, sh) & fullMask) |
 251                            (Ra & ~fullMask); }});
 252     }
 253
 254     // There are a large number of instructions that have the same primary
 255     // opcode (PO) of 31. In this case, the instructions are of different
 256     // forms. For every form, the XO fields may vary in position and width.
 257     // The X, XFL, XFX and XL form instructions use bits 21 - 30 and the
 258     // XO form instructions use bits 22 - 30 as extended opcode (XO). To
 259     // avoid conflicts, instructions of each form have to be defined under
 260     // separate decode blocks. However, only a single decode block can be
 261     // associated with a particular PO and it will recognize only one type
 262     // of XO field. A solution for associating decode blocks for the other
 263     // types of XO fields with the same PO is to have the other blocks as
 264     // nested default cases.
 265     31: decode X_XO {
 266
 267         // All loads with an index register. The non-update versions
 268         // all use the value 0 if Ra == R0, not the value contained in
 269         // R0. Others update Ra with the effective address. In all cases,
 270         // Ra and Rb are source registers, Rt is the destintation.
 271         format LoadIndexOp {
 272             87: lbzx({{ Rt = Mem_ub; }});
 273             52: lbarx({{ Rt = Mem_ub; Rsv = 1; RsvLen = 1; RsvAddr = EA; }});
 274             279: lhzx({{ Rt = Mem_uh; }});
 275             343: lhax({{ Rt = Mem_sh; }});
 276             116: lharx({{ Rt = Mem_uh; Rsv = 1; RsvLen = 2; RsvAddr = EA; }});
 277             790: lhbrx({{ Rt = swap_byte(Mem_uh); }});
 278             23: lwzx({{ Rt = Mem_uw; }});
 279             341: lwax({{ Rt = Mem_sw; }});
 280             20: lwarx({{ Rt = Mem_uw; Rsv = 1; RsvLen = 4; RsvAddr = EA; }});
 281             534: lwbrx({{ Rt = swap_byte(Mem_uw); }});
 282             21: ldx({{ Rt = Mem; }});
 283             84: ldarx({{ Rt = Mem_ud; Rsv = 1; RsvLen = 8; RsvAddr = EA; }});
 284             532: ldbrx({{ Rt = swap_byte(Mem); }});
 285             535: lfsx({{ Ft_sf = Mem_sf; }});
 286             599: lfdx({{ Ft = Mem_df; }});
 287             855: lfiwax({{ Ft_uw = Mem; }});
 288         }
 289
 290         format LoadIndexUpdateOp {
 291             119: lbzux({{ Rt = Mem_ub; }});
 292             311: lhzux({{ Rt = Mem_uh; }});
 293             375: lhaux({{ Rt = Mem_sh; }});
 294             55: lwzux({{ Rt = Mem_uw; }});
 295             373: lwaux({{ Rt = Mem_sw; }});
 296             53: ldux({{ Rt = Mem; }});
 297             567: lfsux({{ Ft_sf = Mem_sf; }});
 298             631: lfdux({{ Ft = Mem_df; }});
 299         }
 300
 301         format StoreIndexOp {
 302             215: stbx({{ Mem_ub = Rs_ub; }});
 303             694: stbcx({{
 304                 bool store_performed = false;
 305                 Mem_ub = Rs_ub;
 306                 if (Rsv) {
 307                     if (RsvLen == 1) {
 308                         if (RsvAddr == EA) {
 309                             store_performed = true;
 310                         }
 311                     }
 312                 }
 313                 Xer xer = XER;
 314                 Cr cr = CR;
 315                 cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
 316                 CR = cr;
 317                 Rsv = 0;
 318             }});
 319             407: sthx({{ Mem_uh = Rs_uh; }});
 320             726: sthcx({{
 321                 bool store_performed = false;
 322                 Mem_uh = Rs_uh;
 323                 if (Rsv) {
 324                     if (RsvLen == 2) {
 325                         if (RsvAddr == EA) {
 326                             store_performed = true;
 327                         }
 328                     }
 329                 }
 330                 Xer xer = XER;
 331                 Cr cr = CR;
 332                 cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
 333                 CR = cr;
 334                 Rsv = 0;
 335             }});
 336             918: sthbrx({{ Mem_uh = swap_byte(Rs_uh); }});
 337             151: stwx({{ Mem_uw = Rs_uw; }});
 338             150: stwcx({{
 339                 bool store_performed = false;
 340                 Mem_uw = Rs_uw;
 341                 if (Rsv) {
 342                     if (RsvLen == 4) {
 343                         if (RsvAddr == EA) {
 344                             store_performed = true;
 345                         }
 346                     }
 347                 }
 348                 Xer xer = XER;
 349                 Cr cr = CR;
 350                 cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
 351                 CR = cr;
 352                 Rsv = 0;
 353             }});
 354             662: stwbrx({{ Mem_uw = swap_byte(Rs_uw); }});
 355             149: stdx({{ Mem = Rs }});
 356             214: stdcx({{
 357                 bool store_performed = false;
 358                 Mem = Rs;
 359                 if (Rsv) {
 360                     if (RsvLen == 8) {
 361                         if (RsvAddr == EA) {
 362                             store_performed = true;
 363                         }
 364                     }
 365                 }
 366                 Xer xer = XER;
 367                 Cr cr = CR;
 368                 cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
 369                 CR = cr;
 370                 Rsv = 0;
 371             }});
 372             660: stdbrx({{ Mem = swap_byte(Rs); }});
 373         }
 374
 375         format StoreIndexUpdateOp {
 376             247: stbux({{ Mem_ub = Rs_ub; }});
 377             439: sthux({{ Mem_uh = Rs_uh; }});
 378             183: stwux({{ Mem_uw = Rs_uw; }});
 379             181: stdux({{ Mem = Rs; }});
 380         }
 381
 382         format IntOp {
 383             0: cmp({{
 384                 Xer xer = XER;
 385                 uint32_t cr = makeCRField(Ra_sw, Rb_sw, xer.so);
 386                 CR = insertCRField(CR, BF, cr);
 387             }});
 388
 389             32: cmpl({{
 390                 Xer xer = XER;
 391                 uint32_t cr = makeCRField(Ra, Rb, xer.so);
 392                 CR = insertCRField(CR, BF, cr);
 393             }});
 394         }
 395
 396         // Integer logic instructions use source registers Rs and Rb,
 397         // with destination register Ra.
 398         format IntLogicOp {
 399             28: and({{ Ra = Rs & Rb; }});
 400             316: xor({{ Ra = Rs ^ Rb; }});
 401             476: nand({{ Ra = ~(Rs & Rb); }});
 402             444: or({{ Ra = Rs | Rb; }});
 403             124: nor({{ Ra = ~(Rs | Rb); }});
 404             60: andc({{ Ra = Rs & ~Rb; }});
 405             954: extsb({{ Ra = sext<8>(Rs); }});
 406             284: eqv({{ Ra = ~(Rs ^ Rb); }});
 407             412: orc({{ Ra = Rs | ~Rb; }});
 408             922: extsh({{ Ra = sext<16>(Rs); }});
 409             26: cntlzw({{ Ra = Rs == 0 ? 32 : 31 - findMsbSet(Rs); }});
 410             508: cmpb({{
 411                 uint32_t val = 0;
 412                 for (int n = 0; n < 32; n += 8) {
 413                     if(bits(Rs, n+7, n) == bits(Rb, n+7, n)) {
 414                         val = insertBits(val, n+7, n, 0xff);
 415                     }
 416                 }
 417                 Ra = val;
 418             }});
 419
 420             24: slw({{
 421                 if (Rb & 0x20) {
 422                     Ra = 0;
 423                 } else {
 424                     Ra = Rs << (Rb & 0x1f);
 425                 }
 426             }});
 427
 428             536: srw({{
 429                 if (Rb & 0x20) {
 430                     Ra = 0;
 431                 } else  {
 432                     Ra = Rs >> (Rb & 0x1f);
 433                 }
 434             }});
 435
 436             792: sraw({{
 437                 bool shiftSetCA = false;
 438                 int32_t s = Rs;
 439                 if (Rb == 0) {
 440                     Ra = Rs;
 441                     shiftSetCA = true;
 442                 } else if (Rb & 0x20) {
 443                     if (s < 0) {
 444                         Ra = (uint32_t)-1;
 445                         if (s & 0x7fffffff) {
 446                             shiftSetCA = true;
 447                         } else {
 448                             shiftSetCA = false;
 449                         }
 450                     } else {
 451                         Ra = 0;
 452                         shiftSetCA = false;
 453                     }
 454                 } else {
 455                     Ra = s >> (Rb & 0x1f);
 456                     if (s < 0 && (s << (32 - (Rb & 0x1f))) != 0) {
 457                         shiftSetCA = true;
 458                     } else {
 459                         shiftSetCA = false;
 460                     }
 461                 }
 462                 Xer xer1 = XER;
 463                 if (shiftSetCA) {
 464                     xer1.ca = 1;
 465                 } else {
 466                     xer1.ca = 0;
 467                 }
 468                 XER = xer1;
 469             }});
 470         }
 471
 472         // Integer logic instructions with a shift value.
 473         format IntShiftOp {
 474             824: srawi({{
 475                 bool shiftSetCA = false;
 476                 if (sh == 0) {
 477                     Ra = Rs;
 478                     shiftSetCA = false;
 479                 } else {
 480                     int32_t s = Rs;
 481                     Ra = s >> sh;
 482                     if (s < 0 && (s << (32 - sh)) != 0) {
 483                         shiftSetCA = true;
 484                     } else {
 485                         shiftSetCA = false;
 486                     }
 487                 }
 488                 Xer xer1 = XER;
 489                 if (shiftSetCA) {
 490                     xer1.ca = 1;
 491                 } else {
 492                     xer1.ca = 0;
 493                 }
 494                 XER = xer1;
 495             }});
 496         }
 497
 498         // Generic integer format instructions.
 499         format IntOp {
 500             339: decode SPR {
 501                 0x20: mfxer({{ Rt = XER; }});
 502                 0x100: mflr({{ Rt = LR; }});
 503                 0x120: mfctr({{ Rt = CTR; }});
 504             }
 505             467: decode SPR {
 506                 0x20: mtxer({{ XER = Rs; }});
 507                 0x100: mtlr({{ LR = Rs; }});
 508                 0x120: mtctr({{ CTR = Rs; }});
 509             }
 510         }
 511
 512         format StoreIndexOp {
 513             663: stfsx({{ Mem_sf = Fs_sf; }});
 514             727: stfdx({{ Mem_df = Fs; }});
 515             983: stfiwx({{ Mem = Fs_uw; }});
 516         }
 517
 518         format StoreIndexUpdateOp {
 519             695: stfsux({{ Mem_sf = Fs_sf; }});
 520             759: stfdux({{ Mem_df = Fs; }});
 521         }
 522
 523         // These instructions all provide data cache hints
 524         format MiscOp {
 525             278: dcbt({{ }});
 526             246: dcbtst({{ }});
 527             598: sync({{ }}, [ IsMemBarrier ]);
 528             854: eieio({{ }}, [ IsMemBarrier ]);
 529         }
 530
 531         // These instructions are of XO form with bit 21 as the OE bit.
 532         default: decode XO_XO {
 533
 534             // These instructions can all be reduced to the form
 535             // Rt = src1 + src2 [+ CA], therefore we just give src1 and src2
 536             // (and, if necessary, CA) definitions and let the python script
 537             // deal with setting things up correctly. We also give flags to
 538             // say which control registers to set.
 539             format IntSumOp {
 540                 266: add({{ Ra }}, {{ Rb }});
 541                 40: subf({{ ~Ra }}, {{ Rb }}, {{ 1 }});
 542                 10: addc({{ Ra }}, {{ Rb }},
 543                          computeCA = true);
 544                 8: subfc({{ ~Ra }}, {{ Rb }}, {{ 1 }},
 545                          true);
 546                 104: neg({{ ~Ra }}, {{ 1 }});
 547                 138: adde({{ Ra }}, {{ Rb }}, {{ xer.ca }},
 548                           true);
 549                 234: addme({{ Ra }}, {{ -1ULL }}, {{ xer.ca }},
 550                            true);
 551                 136: subfe({{ ~Ra }}, {{ Rb }}, {{ xer.ca }},
 552                            true);
 553                 232: subfme({{ ~Ra }}, {{ -1ULL }}, {{ xer.ca }},
 554                             true);
 555                 202: addze({{ Ra }}, {{ xer.ca }},
 556                            computeCA = true);
 557                 200: subfze({{ ~Ra }}, {{ xer.ca }},
 558                             computeCA = true);
 559             }
 560
 561             // Arithmetic instructions all use source registers Ra and Rb,
 562             // with destination register Rt.
 563             format IntArithOp {
 564                 75: mulhw({{
 565                     int64_t prod = Ra_sd * Rb_sd;
 566                     Rt = prod >> 32;
 567                 }});
 568                 11: mulhwu({{
 569                     uint64_t prod = Ra_ud * Rb_ud;
 570                     Rt = prod >> 32;
 571                 }});
 572                 235: mullw({{ int64_t prod = Ra_sd * Rb_sd; Rt = prod; }});
 573                 747: mullwo({{
 574                     int64_t src1 = Ra_sd;
 575                     int64_t src2 = Rb;
 576                     int64_t prod = src1 * src2;
 577                     Rt = prod;
 578                 }},
 579                 true);
 580
 581                 491: divw({{
 582                     int32_t src1 = Ra_sw;
 583                     int32_t src2 = Rb_sw;
 584                     if ((src1 != 0x80000000 || src2 != 0xffffffff)
 585                         && src2 != 0) {
 586                         Rt = src1 / src2;
 587                     } else {
 588                         Rt = 0;
 589                     }
 590                 }});
 591
 592                 1003: divwo({{
 593                     int32_t src1 = Ra_sw;
 594                     int32_t src2 = Rb_sw;
 595                     if ((src1 != 0x80000000 || src2 != 0xffffffff)
 596                         && src2 != 0) {
 597                         Rt = src1 / src2;
 598                     } else {
 599                         Rt = 0;
 600                         divSetOV = true;
 601                     }
 602                 }},
 603                 true);
 604
 605                 459: divwu({{
 606                     uint32_t src1 = Ra_sw;
 607                     uint32_t src2 = Rb_sw;
 608                     if (src2 != 0) {
 609                         Rt = src1 / src2;
 610                     } else {
 611                         Rt = 0;
 612                     }
 613                 }});
 614
 615                 971: divwuo({{
 616                   uint32_t src1 = Ra_sw;
 617                   uint32_t src2 = Rb_sw;
 618                   if (src2 != 0) {
 619                       Rt = src1 / src2;
 620                   } else {
 621                       Rt = 0;
 622                       divSetOV = true;
 623                   }
 624                 }},
 625                 true);
 626             }
 627
 628             default: decode XFX_XO {
 629                 format IntOp {
 630                     144: mtcrf({{
 631                         uint32_t mask = 0;
 632                         for (int i = 0; i < 8; ++i) {
 633                             if (((FXM >> i) & 0x1) == 0x1) {
 634                                 mask |= 0xf << (4 * i);
 635                             }
 636                         }
 637                         CR = (Rs & mask) | (CR & ~mask);
 638                     }});
 639
 640                     19: mfcr({{ Rt = CR; }});
 641                 }
 642             }
 643         }
 644     }
 645
 646     format LoadDispOp {
 647         48: lfs({{ Ft_sf = Mem_sf; }});
 648         50: lfd({{ Ft = Mem_df; }});
 649     }
 650
 651     format LoadDispUpdateOp {
 652         49: lfsu({{ Ft_sf = Mem_sf; }});
 653         51: lfdu({{ Ft = Mem_df; }});
 654     }
 655
 656     format StoreDispOp {
 657         52: stfs({{ Mem_sf = Fs_sf; }});
 658         54: stfd({{ Mem_df = Fs; }});
 659     }
 660
 661     format StoreDispUpdateOp {
 662         53: stfsu({{ Mem_sf = Fs_sf; }});
 663         55: stfdu({{ Mem_df = Fs; }});
 664     }
 665
 666     format FloatArithOp {
 667         59: decode A_XO {
 668             21: fadds({{ Ft = Fa + Fb; }});
 669             20: fsubs({{ Ft = Fa - Fb; }});
 670             25: fmuls({{ Ft = Fa * Fc; }});
 671             18: fdivs({{ Ft = Fa / Fb; }});
 672             29: fmadds({{ Ft = (Fa * Fc) + Fb; }});
 673             28: fmsubs({{ Ft = (Fa * Fc) - Fb; }});
 674             31: fnmadds({{ Ft = -((Fa * Fc) + Fb); }});
 675             30: fnmsubs({{ Ft = -((Fa * Fc) - Fb); }});
 676         }
 677     }
 678
 679     63: decode A_XO {
 680         format FloatArithOp {
 681             21: fadd({{ Ft = Fa + Fb; }});
 682             20: fsub({{ Ft = Fa - Fb; }});
 683             25: fmul({{ Ft = Fa * Fc; }});
 684             18: fdiv({{ Ft = Fa / Fb; }});
 685             29: fmadd({{ Ft = (Fa * Fc) + Fb; }});
 686             28: fmsub({{ Ft = (Fa * Fc) - Fb; }});
 687             31: fnmadd({{ Ft = -((Fa * Fc) + Fb); }});
 688             30: fnmsub({{ Ft = -((Fa * Fc) - Fb); }});
 689         }
 690
 691         default: decode X_XO {
 692             format FloatRCCheckOp {
 693                 72: fmr({{ Ft = Fb; }});
 694                 264: fabs({{
 695                     Ft_ud = Fb_ud;
 696                     Ft_ud = insertBits(Ft_ud, 63, 0); }});
 697                 136: fnabs({{
 698                     Ft_ud = Fb_ud;
 699                     Ft_ud = insertBits(Ft_ud, 63, 1); }});
 700                 40: fneg({{ Ft = -Fb; }});
 701                 8: fcpsgn({{
 702                     Ft_ud = Fb_ud;
 703                     Ft_ud = insertBits(Ft_ud, 63, Fa_ud<63:63>);
 704                 }});
 705             }
 706
 707             format FloatConvertOp {
 708                 12: frsp({{ Ft_sf = Fb; }});
 709                 15: fctiwz({{ Ft_sw = (int32_t)trunc(Fb); }});
 710             }
 711
 712             format FloatOp {
 713               0: fcmpu({{
 714                   uint32_t c = makeCRField(Fa, Fb);
 715                   Fpscr fpscr = FPSCR;
 716                   fpscr.fprf.fpcc = c;
 717                   FPSCR = fpscr;
 718                   CR = insertCRField(CR, BF, c);
 719               }});
 720             }
 721
 722             format FloatRCCheckOp {
 723                 583: mffs({{ Ft_ud = FPSCR; }});
 724                 134: mtfsfi({{
 725                     FPSCR = insertCRField(FPSCR, BF + (8 * (1 - W_FIELD)),
 726                                           U_FIELD);
 727                 }});
 728                 70: mtfsb0({{ FPSCR = insertBits(FPSCR, 31 - BT, 0); }});
 729                 38: mtfsb1({{ FPSCR = insertBits(FPSCR, 31 - BT, 1); }});
 730
 731                 default: decode XFL_XO {
 732                     711: mtfsf({{
 733                         if (L_FIELD == 1) { FPSCR = Fb_ud; }
 734                         else {
 735                             for (int i = 0; i < 8; ++i) {
 736                                 if (bits(FLM, i) == 1) {
 737                                     int k = 4 * (i + (8 * (1 - W_FIELD)));
 738                                     FPSCR = insertBits(FPSCR, k + 3, k,
 739                                                        bits(Fb_ud, k + 3, k));
 740                                 }
 741                             }
 742                         }
 743                     }});
 744                 }
 745             }
 746         }
 747     }
 748 }