src/arch/power/isa/decoder.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2009 The University of Edinburgh
   4 // All rights reserved.
   5 //
   6 // Redistribution and use in source and binary forms, with or without
   7 // modification, are permitted provided that the following conditions are
   8 // met: redistributions of source code must retain the above copyright
   9 // notice, this list of conditions and the following disclaimer;
  10 // redistributions in binary form must reproduce the above copyright
  11 // notice, this list of conditions and the following disclaimer in the
  12 // documentation and/or other materials provided with the distribution;
  13 // neither the name of the copyright holders nor the names of its
  14 // contributors may be used to endorse or promote products derived from
  15 // this software without specific prior written permission.
  16 //
  17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28
  29 ////////////////////////////////////////////////////////////////////
  30 //
  31 // The actual Power ISA decoder
  32 // ------------------------------
  33 //
  34 // I've used the Power ISA Book I v2.06 for instruction formats,
  35 // opcode numbers, register names, etc.
  36 //
  37 decode PO default Unknown::unknown() {
  38
  39     18: decode AA {
  40
  41         // Unconditionally branch relative to PC.
  42         format BranchPCRel {
  43             0: b({{ NIA = (uint32_t)(CIA + disp); }});
  44         }
  45
  46         // Unconditionally branch to fixed address.
  47         format BranchNonPCRel {
  48             1: ba({{ NIA = targetAddr; }});
  49         }
  50     }
  51
  52     16: decode AA {
  53
  54         // Conditionally branch relative to PC based on CR and CTR.
  55         format BranchPCRelCondCtr {
  56             0: bc({{ NIA = (uint32_t)(CIA + disp); }});
  57         }
  58
  59         // Conditionally branch to fixed address based on CR and CTR.
  60         format BranchNonPCRelCondCtr {
  61             1: bca({{ NIA = targetAddr; }});
  62         }
  63     }
  64
  65     19: decode XL_XO {
  66
  67         // Conditionally branch to address in LR based on CR and CTR.
  68         format BranchLrCondCtr {
  69            16: bclr({{ NIA = LR & 0xfffffffc; }});
  70         }
  71
  72         // Conditionally branch to address in CTR based on CR.
  73         format BranchCtrCond {
  74            528: bcctr({{ NIA = CTR & 0xfffffffc; }});
  75         }
  76
  77         // Condition register manipulation instructions.
  78         format CondLogicOp {
  79             257: crand({{
  80                 uint32_t crBa = bits(CR, 31 - ba);
  81                 uint32_t crBb = bits(CR, 31 - bb);
  82                 CR = insertBits(CR, 31 - bt, crBa & crBb);
  83             }});
  84
  85             449: cror({{
  86                 uint32_t crBa = bits(CR, 31 - ba);
  87                 uint32_t crBb = bits(CR, 31 - bb);
  88                 CR = insertBits(CR, 31 - bt, crBa | crBb);
  89             }});
  90
  91             255: crnand({{
  92                 uint32_t crBa = bits(CR, 31 - ba);
  93                 uint32_t crBb = bits(CR, 31 - bb);
  94                 CR = insertBits(CR, 31 - bt, !(crBa & crBb));
  95             }});
  96
  97             193: crxor({{
  98                 uint32_t crBa = bits(CR, 31 - ba);
  99                 uint32_t crBb = bits(CR, 31 - bb);
 100                 CR = insertBits(CR, 31 - bt, crBa ^ crBb);
 101             }});
 102
 103             33: crnor({{
 104                 uint32_t crBa = bits(CR, 31 - ba);
 105                 uint32_t crBb = bits(CR, 31 - bb);
 106                 CR = insertBits(CR, 31 - bt, !(crBa | crBb));
 107             }});
 108
 109             289: creqv({{
 110                 uint32_t crBa = bits(CR, 31 - ba);
 111                 uint32_t crBb = bits(CR, 31 - bb);
 112                 CR = insertBits(CR, 31 - bt, crBa == crBb);
 113             }});
 114
 115             129: crandc({{
 116                 uint32_t crBa = bits(CR, 31 - ba);
 117                 uint32_t crBb = bits(CR, 31 - bb);
 118                 CR = insertBits(CR, 31 - bt, crBa & !crBb);
 119             }});
 120
 121             417: crorc({{
 122                 uint32_t crBa = bits(CR, 31 - ba);
 123                 uint32_t crBb = bits(CR, 31 - bb);
 124                 CR = insertBits(CR, 31 - bt, crBa | !crBb);
 125             }});
 126         }
 127
 128         format CondMoveOp {
 129             0: mcrf({{
 130                 uint32_t crBfa = bits(CR, 31 - bfa*4, 28 - bfa*4);
 131                 CR = insertBits(CR, 31 - bf*4, 28 - bf*4, crBfa);
 132             }});
 133         }
 134
 135         format MiscOp {
 136             150: isync({{ }}, [ IsSerializeAfter ]);
 137         }
 138
 139         default: decode DX_XO {
 140             format IntDispArithOp {
 141                 2: addpcis({{ Rt = NIA + (disp << 16); }});
 142             }
 143         }
 144     }
 145
 146     17: IntOp::sc({{ xc->syscall(R0, &fault); }},
 147                   [ IsSyscall, IsNonSpeculative, IsSerializeAfter ]);
 148
 149     format LoadDispOp {
 150         34: lbz({{ Rt = Mem_ub; }});
 151         40: lhz({{ Rt = Mem_uh; }});
 152         42: lha({{ Rt = Mem_sh; }});
 153         32: lwz({{ Rt = Mem_uw; }});
 154     }
 155
 156     58: decode DS_XO {
 157         format LoadDispShiftOp {
 158             2: lwa({{ Rt = Mem_sw; }});
 159             0: ld({{ Rt = Mem; }});
 160         }
 161
 162         format LoadDispShiftUpdateOp {
 163             1: ldu({{ Rt = Mem; }});
 164         }
 165     }
 166
 167     62: decode DS_XO {
 168         format StoreDispShiftOp {
 169             0: std({{ Mem = Rs; }});
 170         }
 171
 172         format StoreDispShiftUpdateOp {
 173             1: stdu({{ Mem = Rs; }});
 174         }
 175     }
 176
 177     format LoadDispUpdateOp {
 178         35: lbzu({{ Rt = Mem_ub; }});
 179         41: lhzu({{ Rt = Mem_uh; }});
 180         43: lhau({{ Rt = Mem_sh; }});
 181         33: lwzu({{ Rt = Mem_uw; }});
 182     }
 183
 184     format StoreDispOp {
 185         38: stb({{ Mem_ub = Rs_ub; }});
 186         44: sth({{ Mem_uh = Rs_uh; }});
 187         36: stw({{ Mem = Rs_uw; }});
 188     }
 189
 190     format StoreDispUpdateOp {
 191         39: stbu({{ Mem_ub = Rs_ub; }});
 192         45: sthu({{ Mem_uh = Rs_uh; }});
 193         37: stwu({{ Mem = Rs_uw; }});
 194     }
 195
 196     format IntImmArithCheckRaOp {
 197         14: addi({{ Rt = Ra + simm; }},
 198                  {{ Rt = simm }});
 199         15: addis({{ Rt = Ra + (simm << 16); }},
 200                   {{ Rt = simm << 16; }});
 201     }
 202
 203     format IntImmArithOp {
 204         12: addic({{
 205             uint64_t src = Ra;
 206             Rt = src + simm;
 207         }},
 208         true);
 209
 210         13: addic_({{
 211             uint64_t src = Ra;
 212             Rt = src + simm;
 213         }},
 214         true, true);
 215
 216         8: subfic({{
 217             uint64_t src = ~Ra;
 218             Rt = src + simm + 1;
 219         }},
 220         true);
 221
 222         7: mulli({{
 223             int64_t res = Ra_sd * simm;
 224             Rt = res;
 225         }});
 226     }
 227
 228     format IntImmOp {
 229         10: cmpli({{
 230             Xer xer = XER;
 231             uint32_t cr = makeCRField(Ra, (uint32_t)uimm, xer.so);
 232             CR = insertCRField(CR, BF, cr);
 233             }});
 234         11: cmpi({{
 235             Xer xer = XER;
 236             uint32_t cr = makeCRField(Ra_sw, (int32_t)imm, xer.so);
 237             CR = insertCRField(CR, BF, cr);
 238             }});
 239     }
 240
 241     format IntImmLogicOp {
 242         24: ori({{ Ra = Rs | uimm; }});
 243         25: oris({{ Ra = Rs | (uimm << 16); }});
 244         26: xori({{ Ra = Rs ^ uimm; }});
 245         27: xoris({{ Ra = Rs ^ (uimm << 16); }});
 246         28: andi_({{ Ra = Rs & uimm; }},
 247                   true);
 248         29: andis_({{ Ra = Rs & (uimm << 16); }},
 249                    true);
 250     }
 251
 252     format IntRotateOp {
 253         21: rlwinm({{ Ra = rotateValue(Rs, sh) & fullMask; }});
 254         23: rlwnm({{ Ra = rotateValue(Rs, Rb) & fullMask; }});
 255         20: rlwimi({{ Ra = (rotateValue(Rs, sh) & fullMask) |
 256                            (Ra & ~fullMask); }});
 257     }
 258
 259     // There are a large number of instructions that have the same primary
 260     // opcode (PO) of 31. In this case, the instructions are of different
 261     // forms. For every form, the XO fields may vary in position and width.
 262     // The X, XFL, XFX and XL form instructions use bits 21 - 30 and the
 263     // XO form instructions use bits 22 - 30 as extended opcode (XO). To
 264     // avoid conflicts, instructions of each form have to be defined under
 265     // separate decode blocks. However, only a single decode block can be
 266     // associated with a particular PO and it will recognize only one type
 267     // of XO field. A solution for associating decode blocks for the other
 268     // types of XO fields with the same PO is to have the other blocks as
 269     // nested default cases.
 270     31: decode X_XO {
 271
 272         // All loads with an index register. The non-update versions
 273         // all use the value 0 if Ra == R0, not the value contained in
 274         // R0. Others update Ra with the effective address. In all cases,
 275         // Ra and Rb are source registers, Rt is the destintation.
 276         format LoadIndexOp {
 277             87: lbzx({{ Rt = Mem_ub; }});
 278             52: lbarx({{ Rt = Mem_ub; Rsv = 1; RsvLen = 1; RsvAddr = EA; }});
 279             279: lhzx({{ Rt = Mem_uh; }});
 280             343: lhax({{ Rt = Mem_sh; }});
 281             116: lharx({{ Rt = Mem_uh; Rsv = 1; RsvLen = 2; RsvAddr = EA; }});
 282             790: lhbrx({{ Rt = swap_byte(Mem_uh); }});
 283             23: lwzx({{ Rt = Mem_uw; }});
 284             341: lwax({{ Rt = Mem_sw; }});
 285             20: lwarx({{ Rt = Mem_uw; Rsv = 1; RsvLen = 4; RsvAddr = EA; }});
 286             534: lwbrx({{ Rt = swap_byte(Mem_uw); }});
 287             21: ldx({{ Rt = Mem; }});
 288             84: ldarx({{ Rt = Mem_ud; Rsv = 1; RsvLen = 8; RsvAddr = EA; }});
 289             532: ldbrx({{ Rt = swap_byte(Mem); }});
 290             535: lfsx({{ Ft_sf = Mem_sf; }});
 291             599: lfdx({{ Ft = Mem_df; }});
 292             855: lfiwax({{ Ft_uw = Mem; }});
 293         }
 294
 295         format LoadIndexUpdateOp {
 296             119: lbzux({{ Rt = Mem_ub; }});
 297             311: lhzux({{ Rt = Mem_uh; }});
 298             375: lhaux({{ Rt = Mem_sh; }});
 299             55: lwzux({{ Rt = Mem_uw; }});
 300             373: lwaux({{ Rt = Mem_sw; }});
 301             53: ldux({{ Rt = Mem; }});
 302             567: lfsux({{ Ft_sf = Mem_sf; }});
 303             631: lfdux({{ Ft = Mem_df; }});
 304         }
 305
 306         format StoreIndexOp {
 307             215: stbx({{ Mem_ub = Rs_ub; }});
 308             694: stbcx({{
 309                 bool store_performed = false;
 310                 Mem_ub = Rs_ub;
 311                 if (Rsv) {
 312                     if (RsvLen == 1) {
 313                         if (RsvAddr == EA) {
 314                             store_performed = true;
 315                         }
 316                     }
 317                 }
 318                 Xer xer = XER;
 319                 Cr cr = CR;
 320                 cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
 321                 CR = cr;
 322                 Rsv = 0;
 323             }});
 324             407: sthx({{ Mem_uh = Rs_uh; }});
 325             726: sthcx({{
 326                 bool store_performed = false;
 327                 Mem_uh = Rs_uh;
 328                 if (Rsv) {
 329                     if (RsvLen == 2) {
 330                         if (RsvAddr == EA) {
 331                             store_performed = true;
 332                         }
 333                     }
 334                 }
 335                 Xer xer = XER;
 336                 Cr cr = CR;
 337                 cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
 338                 CR = cr;
 339                 Rsv = 0;
 340             }});
 341             918: sthbrx({{ Mem_uh = swap_byte(Rs_uh); }});
 342             151: stwx({{ Mem_uw = Rs_uw; }});
 343             150: stwcx({{
 344                 bool store_performed = false;
 345                 Mem_uw = Rs_uw;
 346                 if (Rsv) {
 347                     if (RsvLen == 4) {
 348                         if (RsvAddr == EA) {
 349                             store_performed = true;
 350                         }
 351                     }
 352                 }
 353                 Xer xer = XER;
 354                 Cr cr = CR;
 355                 cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
 356                 CR = cr;
 357                 Rsv = 0;
 358             }});
 359             662: stwbrx({{ Mem_uw = swap_byte(Rs_uw); }});
 360             149: stdx({{ Mem = Rs }});
 361             214: stdcx({{
 362                 bool store_performed = false;
 363                 Mem = Rs;
 364                 if (Rsv) {
 365                     if (RsvLen == 8) {
 366                         if (RsvAddr == EA) {
 367                             store_performed = true;
 368                         }
 369                     }
 370                 }
 371                 Xer xer = XER;
 372                 Cr cr = CR;
 373                 cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
 374                 CR = cr;
 375                 Rsv = 0;
 376             }});
 377             660: stdbrx({{ Mem = swap_byte(Rs); }});
 378         }
 379
 380         format StoreIndexUpdateOp {
 381             247: stbux({{ Mem_ub = Rs_ub; }});
 382             439: sthux({{ Mem_uh = Rs_uh; }});
 383             183: stwux({{ Mem_uw = Rs_uw; }});
 384             181: stdux({{ Mem = Rs; }});
 385         }
 386
 387         format IntArithOp {
 388             779: modsw({{
 389                 int64_t src1 = Ra_sw;
 390                 int64_t src2 = Rb_sw;
 391                 if ((src1 != INT32_MIN || src2 != -1) && src2 != 0) {
 392                     Rt = src1 % src2;
 393                 } else {
 394                     Rt = 0;
 395                 }
 396             }});
 397
 398             267: moduw({{
 399                 uint64_t src1 = Ra_uw;
 400                 uint64_t src2 = Rb_uw;
 401                 if (src2 != 0) {
 402                     Rt = src1 % src2;
 403                 } else {
 404                     Rt = 0;
 405                 }
 406             }});
 407         }
 408
 409         format IntOp {
 410             0: cmp({{
 411                 Xer xer = XER;
 412                 uint32_t cr = makeCRField(Ra_sw, Rb_sw, xer.so);
 413                 CR = insertCRField(CR, BF, cr);
 414             }});
 415
 416             32: cmpl({{
 417                 Xer xer = XER;
 418                 uint32_t cr = makeCRField(Ra, Rb, xer.so);
 419                 CR = insertCRField(CR, BF, cr);
 420             }});
 421         }
 422
 423         // Integer logic instructions use source registers Rs and Rb,
 424         // with destination register Ra.
 425         format IntLogicOp {
 426             28: and({{ Ra = Rs & Rb; }});
 427             316: xor({{ Ra = Rs ^ Rb; }});
 428             476: nand({{ Ra = ~(Rs & Rb); }});
 429             444: or({{ Ra = Rs | Rb; }});
 430             124: nor({{ Ra = ~(Rs | Rb); }});
 431             60: andc({{ Ra = Rs & ~Rb; }});
 432             954: extsb({{ Ra = sext<8>(Rs); }});
 433             284: eqv({{ Ra = ~(Rs ^ Rb); }});
 434             412: orc({{ Ra = Rs | ~Rb; }});
 435             922: extsh({{ Ra = sext<16>(Rs); }});
 436             26: cntlzw({{ Ra = Rs == 0 ? 32 : 31 - findMsbSet(Rs); }});
 437             508: cmpb({{
 438                 uint32_t val = 0;
 439                 for (int n = 0; n < 32; n += 8) {
 440                     if(bits(Rs, n+7, n) == bits(Rb, n+7, n)) {
 441                         val = insertBits(val, n+7, n, 0xff);
 442                     }
 443                 }
 444                 Ra = val;
 445             }});
 446
 447             24: slw({{
 448                 if (Rb & 0x20) {
 449                     Ra = 0;
 450                 } else {
 451                     Ra = Rs << (Rb & 0x1f);
 452                 }
 453             }});
 454
 455             536: srw({{
 456                 if (Rb & 0x20) {
 457                     Ra = 0;
 458                 } else  {
 459                     Ra = Rs >> (Rb & 0x1f);
 460                 }
 461             }});
 462
 463             792: sraw({{
 464                 bool shiftSetCA = false;
 465                 int32_t s = Rs;
 466                 if (Rb == 0) {
 467                     Ra = Rs;
 468                     shiftSetCA = true;
 469                 } else if (Rb & 0x20) {
 470                     if (s < 0) {
 471                         Ra = (uint32_t)-1;
 472                         if (s & 0x7fffffff) {
 473                             shiftSetCA = true;
 474                         } else {
 475                             shiftSetCA = false;
 476                         }
 477                     } else {
 478                         Ra = 0;
 479                         shiftSetCA = false;
 480                     }
 481                 } else {
 482                     Ra = s >> (Rb & 0x1f);
 483                     if (s < 0 && (s << (32 - (Rb & 0x1f))) != 0) {
 484                         shiftSetCA = true;
 485                     } else {
 486                         shiftSetCA = false;
 487                     }
 488                 }
 489                 Xer xer1 = XER;
 490                 if (shiftSetCA) {
 491                     xer1.ca = 1;
 492                 } else {
 493                     xer1.ca = 0;
 494                 }
 495                 XER = xer1;
 496             }});
 497         }
 498
 499         // Integer logic instructions with a shift value.
 500         format IntShiftOp {
 501             824: srawi({{
 502                 bool shiftSetCA = false;
 503                 if (sh == 0) {
 504                     Ra = Rs;
 505                     shiftSetCA = false;
 506                 } else {
 507                     int32_t s = Rs;
 508                     Ra = s >> sh;
 509                     if (s < 0 && (s << (32 - sh)) != 0) {
 510                         shiftSetCA = true;
 511                     } else {
 512                         shiftSetCA = false;
 513                     }
 514                 }
 515                 Xer xer1 = XER;
 516                 if (shiftSetCA) {
 517                     xer1.ca = 1;
 518                 } else {
 519                     xer1.ca = 0;
 520                 }
 521                 XER = xer1;
 522             }});
 523         }
 524
 525         // Generic integer format instructions.
 526         format IntOp {
 527             339: decode SPR {
 528                 0x20: mfxer({{ Rt = XER; }});
 529                 0x100: mflr({{ Rt = LR; }});
 530                 0x120: mfctr({{ Rt = CTR; }});
 531             }
 532             467: decode SPR {
 533                 0x20: mtxer({{ XER = Rs; }});
 534                 0x100: mtlr({{ LR = Rs; }});
 535                 0x120: mtctr({{ CTR = Rs; }});
 536             }
 537         }
 538
 539         format StoreIndexOp {
 540             663: stfsx({{ Mem_sf = Fs_sf; }});
 541             727: stfdx({{ Mem_df = Fs; }});
 542             983: stfiwx({{ Mem = Fs_uw; }});
 543         }
 544
 545         format StoreIndexUpdateOp {
 546             695: stfsux({{ Mem_sf = Fs_sf; }});
 547             759: stfdux({{ Mem_df = Fs; }});
 548         }
 549
 550         // These instructions all provide data cache hints
 551         format MiscOp {
 552             278: dcbt({{ }});
 553             246: dcbtst({{ }});
 554             598: sync({{ }}, [ IsMemBarrier ]);
 555             854: eieio({{ }}, [ IsMemBarrier ]);
 556         }
 557
 558         // These instructions are of XO form with bit 21 as the OE bit.
 559         default: decode XO_XO {
 560
 561             // These instructions can all be reduced to the form
 562             // Rt = src1 + src2 [+ CA], therefore we just give src1 and src2
 563             // (and, if necessary, CA) definitions and let the python script
 564             // deal with setting things up correctly. We also give flags to
 565             // say which control registers to set.
 566             format IntSumOp {
 567                 266: add({{ Ra }}, {{ Rb }});
 568                 40: subf({{ ~Ra }}, {{ Rb }}, {{ 1 }});
 569                 10: addc({{ Ra }}, {{ Rb }},
 570                          computeCA = true);
 571                 8: subfc({{ ~Ra }}, {{ Rb }}, {{ 1 }},
 572                          true);
 573                 104: neg({{ ~Ra }}, {{ 1 }});
 574                 138: adde({{ Ra }}, {{ Rb }}, {{ xer.ca }},
 575                           true);
 576                 234: addme({{ Ra }}, {{ -1ULL }}, {{ xer.ca }},
 577                            true);
 578                 136: subfe({{ ~Ra }}, {{ Rb }}, {{ xer.ca }},
 579                            true);
 580                 232: subfme({{ ~Ra }}, {{ -1ULL }}, {{ xer.ca }},
 581                             true);
 582                 202: addze({{ Ra }}, {{ xer.ca }},
 583                            computeCA = true);
 584                 200: subfze({{ ~Ra }}, {{ xer.ca }},
 585                             computeCA = true);
 586             }
 587
 588             // Arithmetic instructions all use source registers Ra and Rb,
 589             // with destination register Rt.
 590             format IntArithCheckRcOp {
 591                 75: mulhw({{
 592                     uint64_t res = (int64_t)Ra_sw * Rb_sw;
 593                     res = res >> 32;
 594                     Rt = res;
 595                 }});
 596
 597                 11: mulhwu({{
 598                     uint64_t res = (uint64_t)Ra_uw * Rb_uw;
 599                     res = res >> 32;
 600                     Rt = res;
 601                 }});
 602
 603                 235: mullw({{
 604                     int64_t res = (int64_t)Ra_sw * Rb_sw;
 605                     if (res != (int32_t)res) {
 606                         setOV = true;
 607                     }
 608                     Rt = res;
 609                 }},
 610                 true);
 611
 612                 491: divw({{
 613                     int32_t src1 = Ra_sw;
 614                     int32_t src2 = Rb_sw;
 615                     if ((src1 != INT32_MIN || src2 != -1) && src2 != 0) {
 616                         Rt = (uint32_t)(src1 / src2);
 617                     } else {
 618                         Rt = 0;
 619                         setOV = true;
 620                     }
 621                 }},
 622                 true);
 623
 624                 459: divwu({{
 625                     uint32_t src1 = Ra_uw;
 626                     uint32_t src2 = Rb_uw;
 627                     if (src2 != 0) {
 628                         Rt = src1 / src2;
 629                     } else {
 630                         Rt = 0;
 631                         setOV = true;
 632                     }
 633                 }},
 634                 true);
 635
 636                 427: divwe({{
 637                     int32_t src1 = Ra_sw;
 638                     int32_t src2 = Rb_sw;
 639                     int64_t res;
 640                     if ((src1 != INT32_MIN || src2 != -1) && src2 != 0) {
 641                         res = ((int64_t)src1 << 32) / src2;
 642                         if (res == (int32_t)res) {
 643                             Rt = (uint32_t)res;
 644                         } else {
 645                             Rt = 0;
 646                             setOV = true;
 647                         }
 648                     } else {
 649                         Rt = 0;
 650                         setOV = true;
 651                     }
 652                 }},
 653                 true);
 654
 655                 395: divweu({{
 656                     uint32_t src1 = Ra_ud;
 657                     uint32_t src2 = Rb_ud;
 658                     uint64_t res;
 659                     if (src2 != 0) {
 660                         res = ((uint64_t)src1 << 32) / src2;
 661                         if (res <= UINT32_MAX) {
 662                             Rt = (uint32_t)res;
 663                         } else {
 664                             Rt = 0;
 665                             setOV = true;
 666                         }
 667                     } else {
 668                         Rt = 0;
 669                         setOV = true;
 670                     }
 671                 }},
 672                 true);
 673             }
 674
 675             default: decode XFX_XO {
 676                 format IntOp {
 677                     144: mtcrf({{
 678                         uint32_t mask = 0;
 679                         for (int i = 0; i < 8; ++i) {
 680                             if (((FXM >> i) & 0x1) == 0x1) {
 681                                 mask |= 0xf << (4 * i);
 682                             }
 683                         }
 684                         CR = (Rs & mask) | (CR & ~mask);
 685                     }});
 686
 687                     19: mfcr({{ Rt = CR; }});
 688                 }
 689             }
 690         }
 691     }
 692
 693     format LoadDispOp {
 694         48: lfs({{ Ft_sf = Mem_sf; }});
 695         50: lfd({{ Ft = Mem_df; }});
 696     }
 697
 698     format LoadDispUpdateOp {
 699         49: lfsu({{ Ft_sf = Mem_sf; }});
 700         51: lfdu({{ Ft = Mem_df; }});
 701     }
 702
 703     format StoreDispOp {
 704         52: stfs({{ Mem_sf = Fs_sf; }});
 705         54: stfd({{ Mem_df = Fs; }});
 706     }
 707
 708     format StoreDispUpdateOp {
 709         53: stfsu({{ Mem_sf = Fs_sf; }});
 710         55: stfdu({{ Mem_df = Fs; }});
 711     }
 712
 713     format FloatArithOp {
 714         59: decode A_XO {
 715             21: fadds({{ Ft = Fa + Fb; }});
 716             20: fsubs({{ Ft = Fa - Fb; }});
 717             25: fmuls({{ Ft = Fa * Fc; }});
 718             18: fdivs({{ Ft = Fa / Fb; }});
 719             29: fmadds({{ Ft = (Fa * Fc) + Fb; }});
 720             28: fmsubs({{ Ft = (Fa * Fc) - Fb; }});
 721             31: fnmadds({{ Ft = -((Fa * Fc) + Fb); }});
 722             30: fnmsubs({{ Ft = -((Fa * Fc) - Fb); }});
 723         }
 724     }
 725
 726     63: decode A_XO {
 727         format FloatArithOp {
 728             21: fadd({{ Ft = Fa + Fb; }});
 729             20: fsub({{ Ft = Fa - Fb; }});
 730             25: fmul({{ Ft = Fa * Fc; }});
 731             18: fdiv({{ Ft = Fa / Fb; }});
 732             29: fmadd({{ Ft = (Fa * Fc) + Fb; }});
 733             28: fmsub({{ Ft = (Fa * Fc) - Fb; }});
 734             31: fnmadd({{ Ft = -((Fa * Fc) + Fb); }});
 735             30: fnmsub({{ Ft = -((Fa * Fc) - Fb); }});
 736         }
 737
 738         default: decode X_XO {
 739             format FloatRCCheckOp {
 740                 72: fmr({{ Ft = Fb; }});
 741                 264: fabs({{
 742                     Ft_ud = Fb_ud;
 743                     Ft_ud = insertBits(Ft_ud, 63, 0); }});
 744                 136: fnabs({{
 745                     Ft_ud = Fb_ud;
 746                     Ft_ud = insertBits(Ft_ud, 63, 1); }});
 747                 40: fneg({{ Ft = -Fb; }});
 748                 8: fcpsgn({{
 749                     Ft_ud = Fb_ud;
 750                     Ft_ud = insertBits(Ft_ud, 63, Fa_ud<63:63>);
 751                 }});
 752             }
 753
 754             format FloatConvertOp {
 755                 12: frsp({{ Ft_sf = Fb; }});
 756                 15: fctiwz({{ Ft_sw = (int32_t)trunc(Fb); }});
 757             }
 758
 759             format FloatOp {
 760               0: fcmpu({{
 761                   uint32_t c = makeCRField(Fa, Fb);
 762                   Fpscr fpscr = FPSCR;
 763                   fpscr.fprf.fpcc = c;
 764                   FPSCR = fpscr;
 765                   CR = insertCRField(CR, BF, c);
 766               }});
 767             }
 768
 769             format FloatRCCheckOp {
 770                 583: mffs({{ Ft_ud = FPSCR; }});
 771                 134: mtfsfi({{
 772                     FPSCR = insertCRField(FPSCR, BF + (8 * (1 - W_FIELD)),
 773                                           U_FIELD);
 774                 }});
 775                 70: mtfsb0({{ FPSCR = insertBits(FPSCR, 31 - BT, 0); }});
 776                 38: mtfsb1({{ FPSCR = insertBits(FPSCR, 31 - BT, 1); }});
 777
 778                 default: decode XFL_XO {
 779                     711: mtfsf({{
 780                         if (L_FIELD == 1) { FPSCR = Fb_ud; }
 781                         else {
 782                             for (int i = 0; i < 8; ++i) {
 783                                 if (bits(FLM, i) == 1) {
 784                                     int k = 4 * (i + (8 * (1 - W_FIELD)));
 785                                     FPSCR = insertBits(FPSCR, k + 3, k,
 786                                                        bits(Fb_ud, k + 3, k));
 787                                 }
 788                             }
 789                         }
 790                     }});
 791                 }
 792             }
 793         }
 794     }
 795 }