src/arch/power/isa/decoder.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2009 The University of Edinburgh
   4 // All rights reserved.
   5 //
   6 // Redistribution and use in source and binary forms, with or without
   7 // modification, are permitted provided that the following conditions are
   8 // met: redistributions of source code must retain the above copyright
   9 // notice, this list of conditions and the following disclaimer;
  10 // redistributions in binary form must reproduce the above copyright
  11 // notice, this list of conditions and the following disclaimer in the
  12 // documentation and/or other materials provided with the distribution;
  13 // neither the name of the copyright holders nor the names of its
  14 // contributors may be used to endorse or promote products derived from
  15 // this software without specific prior written permission.
  16 //
  17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28
  29 ////////////////////////////////////////////////////////////////////
  30 //
  31 // The actual Power ISA decoder
  32 // ------------------------------
  33 //
  34 // I've used the Power ISA Book I v2.06 for instruction formats,
  35 // opcode numbers, register names, etc.
  36 //
  37 decode PO default Unknown::unknown() {
  38
  39     // Unconditionally branch to a PC-relative or absoulute address.
  40     format BranchOp {
  41         18: b({{ NIA = CIA + disp; }},
  42               {{ NIA = disp; }});
  43     }
  44
  45     // Conditionally branch to a PC-relative or absoulute address based
  46     // on CR and CTR.
  47     format BranchDispCondOp {
  48         16: bc({{ NIA = CIA + disp; }},
  49                {{ NIA = disp; }});
  50     }
  51
  52     19: decode XL_XO {
  53
  54         // Conditionally branch to an address in a register based on
  55         // either CR only or both CR and CTR.
  56         format BranchRegCondOp {
  57             16: bclr({{ NIA = LR & -4ULL; }}, true, [ IsReturn ]);
  58             528: bcctr({{ NIA = CTR & -4ULL; }});
  59             560: bctar({{ NIA = TAR & -4ULL; }}, true);
  60         }
  61
  62         // Condition register manipulation instructions.
  63         format CondLogicOp {
  64             257: crand({{
  65                 uint32_t crBa = bits(CR, 31 - ba);
  66                 uint32_t crBb = bits(CR, 31 - bb);
  67                 CR = insertBits(CR, 31 - bt, crBa & crBb);
  68             }});
  69
  70             449: cror({{
  71                 uint32_t crBa = bits(CR, 31 - ba);
  72                 uint32_t crBb = bits(CR, 31 - bb);
  73                 CR = insertBits(CR, 31 - bt, crBa | crBb);
  74             }});
  75
  76             255: crnand({{
  77                 uint32_t crBa = bits(CR, 31 - ba);
  78                 uint32_t crBb = bits(CR, 31 - bb);
  79                 CR = insertBits(CR, 31 - bt, !(crBa & crBb));
  80             }});
  81
  82             193: crxor({{
  83                 uint32_t crBa = bits(CR, 31 - ba);
  84                 uint32_t crBb = bits(CR, 31 - bb);
  85                 CR = insertBits(CR, 31 - bt, crBa ^ crBb);
  86             }});
  87
  88             33: crnor({{
  89                 uint32_t crBa = bits(CR, 31 - ba);
  90                 uint32_t crBb = bits(CR, 31 - bb);
  91                 CR = insertBits(CR, 31 - bt, !(crBa | crBb));
  92             }});
  93
  94             289: creqv({{
  95                 uint32_t crBa = bits(CR, 31 - ba);
  96                 uint32_t crBb = bits(CR, 31 - bb);
  97                 CR = insertBits(CR, 31 - bt, crBa == crBb);
  98             }});
  99
 100             129: crandc({{
 101                 uint32_t crBa = bits(CR, 31 - ba);
 102                 uint32_t crBb = bits(CR, 31 - bb);
 103                 CR = insertBits(CR, 31 - bt, crBa & !crBb);
 104             }});
 105
 106             417: crorc({{
 107                 uint32_t crBa = bits(CR, 31 - ba);
 108                 uint32_t crBb = bits(CR, 31 - bb);
 109                 CR = insertBits(CR, 31 - bt, crBa | !crBb);
 110             }});
 111         }
 112
 113         format CondMoveOp {
 114             0: mcrf({{
 115                 uint32_t crBfa = bits(CR, 31 - bfa*4, 28 - bfa*4);
 116                 CR = insertBits(CR, 31 - bf*4, 28 - bf*4, crBfa);
 117             }});
 118         }
 119
 120         format MiscOp {
 121             150: isync({{ }}, [ IsSerializeAfter ]);
 122
 123             18:  rfid({{
 124                 uint32_t msr12=(bits(MSR,60)&bits(SRR1,12))
 125                                |((bits(MSR,60)^0x01)&bits(MSR,12));
 126                 MSR = insertBits(MSR,12,msr12);
 127                 uint32_t msr60=bits(MSR,60)&bits(SRR1,60);
 128                 MSR = insertBits(MSR,60,msr60);
 129                 if((bits(MSR,34,32)!=0x02)|(bits(SRR1,34,32)!=0x00))
 130                     MSR = insertBits(MSR,34,32,bits(SRR1,34,32));
 131                 MSR = insertBits(MSR,15,(bits(SRR1,15)|bits(SRR1,14)));
 132                 MSR = insertBits(MSR,5,(bits(SRR1,5)|bits(SRR1,14)));
 133                 MSR = insertBits(MSR,4,(bits(SRR1,4)|bits(SRR1,14)));
 134                 MSR = insertBits(MSR,63,61,bits(SRR1,63,61));
 135                 MSR = insertBits(MSR,59,35,bits(SRR1,59,35));
 136                 MSR = insertBits(MSR,31,bits(SRR1,31));
 137                 MSR = insertBits(MSR,26,22,bits(SRR1,26,22));
 138                 MSR = insertBits(MSR,14,13,bits(SRR1,14,13));
 139                 MSR = insertBits(MSR,11,6,bits(SRR1,11,6));
 140                 MSR = insertBits(MSR,3,0,bits(SRR1,3,0));
 141                 NIA = SRR0 & -4ULL;
 142             }}, [ IsPrivileged ]);
 143             274:  hrfid({{
 144                 if((bits(MSR,34,32)!=0x02)|(bits(HSRR1,34,32)!=0x00))
 145                     MSR = insertBits(MSR,34,32,bits(HSRR1,34,32));
 146                 MSR = insertBits(MSR,15,(bits(HSRR1,15)|bits(HSRR1,14)));
 147                 MSR = insertBits(MSR,5,(bits(HSRR1,5)|bits(HSRR1,14)));
 148                 MSR = insertBits(MSR,4,(bits(HSRR1,4)|bits(HSRR1,14)));
 149                 MSR = insertBits(MSR,63,35,bits(HSRR1,63,35));
 150                 MSR = insertBits(MSR,31,bits(HSRR1,31));
 151                 MSR = insertBits(MSR,26,22,bits(HSRR1,26,22));
 152                 MSR = insertBits(MSR,14,6,bits(HSRR1,14,6));
 153                 MSR = insertBits(MSR,3,0,bits(HSRR1,3,0));
 154                 NIA = HSRR0 & -4ULL;
 155             }});
 156         }
 157
 158         default: decode DX_XO {
 159             format IntDispArithOp {
 160                 2: addpcis({{ Rt = NIA + (disp << 16); }});
 161             }
 162         }
 163     }
 164
 165 //TODO:Right now sc instruction not handles LEV=1 case
 166
 167     format IntOp {
 168         17: sc({{
 169             if (FullSystem) {
 170                 fault= std::make_shared<SystemCallInterrupt>();
 171             } else {
 172                 xc->syscall(R0, &fault);
 173             }
 174             }},
 175               [ IsSyscall, IsNonSpeculative, IsSerializeAfter ]);
 176         2: tdi({{ }});
 177     }
 178
 179     format LoadDispOp {
 180         34: lbz({{ Rt = Mem_ub; }});
 181         40: lhz({{ Rt = Mem_uh; }});
 182         42: lha({{ Rt = Mem_sh; }});
 183         32: lwz({{ Rt = Mem_uw; }});
 184     }
 185
 186     58: decode DS_XO {
 187         format LoadDispShiftOp {
 188             2: lwa({{ Rt = Mem_sw; }});
 189             0: ld({{ Rt = Mem; }});
 190         }
 191
 192         format LoadDispShiftUpdateOp {
 193             1: ldu({{ Rt = Mem; }});
 194         }
 195     }
 196
 197     62: decode DS_XO {
 198         format StoreDispShiftOp {
 199             0: std({{ Mem = Rs; }});
 200         }
 201
 202         format StoreDispShiftUpdateOp {
 203             1: stdu({{ Mem = Rs; }});
 204         }
 205     }
 206
 207     format LoadDispUpdateOp {
 208         35: lbzu({{ Rt = Mem_ub; }});
 209         41: lhzu({{ Rt = Mem_uh; }});
 210         43: lhau({{ Rt = Mem_sh; }});
 211         33: lwzu({{ Rt = Mem_uw; }});
 212     }
 213
 214     format StoreDispOp {
 215         38: stb({{ Mem_ub = Rs_ub; }});
 216         44: sth({{ Mem_uh = Rs_uh; }});
 217         36: stw({{ Mem = Rs_uw; }});
 218     }
 219
 220     format StoreDispUpdateOp {
 221         39: stbu({{ Mem_ub = Rs_ub; }});
 222         45: sthu({{ Mem_uh = Rs_uh; }});
 223         37: stwu({{ Mem = Rs_uw; }});
 224     }
 225
 226     format IntImmArithCheckRaOp {
 227         14: addi({{ Rt = Ra + simm; }},
 228                  {{ Rt = simm }});
 229         15: addis({{ Rt = Ra + (simm << 16); }},
 230                   {{ Rt = simm << 16; }});
 231     }
 232
 233     format IntImmArithOp {
 234         12: addic({{
 235             uint64_t src = Ra;
 236             Rt = src + simm;
 237         }},
 238         true);
 239
 240         13: addic_({{
 241             uint64_t src = Ra;
 242             Rt = src + simm;
 243         }},
 244         true, true);
 245
 246         8: subfic({{
 247             uint64_t src = ~Ra;
 248             Rt = src + simm + 1;
 249         }},
 250         true);
 251
 252         7: mulli({{
 253             int64_t res = Ra_sd * simm;
 254             Rt = res;
 255         }});
 256     }
 257
 258     4: decode VA_XO {
 259
 260         // Arithmetic instructions that use source registers Ra, Rb and Rc,
 261         // with destination register Rt.
 262         format IntArithOp {
 263             48: maddhd({{
 264                 int64_t res;
 265                 std::tie(std::ignore, res) = multiplyAdd(Ra_sd, Rb_sd, Rc_sd);
 266                 Rt = res;
 267             }});
 268
 269             49: maddhdu({{
 270                 uint64_t res;
 271                 std::tie(std::ignore, res) = multiplyAdd(Ra, Rb, Rc);
 272                 Rt = res;
 273             }});
 274
 275             51: maddld({{
 276                 uint64_t res;
 277                 std::tie(res, std::ignore) = multiplyAdd(Ra_sd, Rb_sd, Rc_sd);
 278                 Rt = res;
 279             }});
 280         }
 281     }
 282
 283     format IntImmCompOp {
 284         11: cmpi({{
 285             if (length) {
 286                 cr = makeCRField(Ra_sd, simm, xer.so);
 287             } else {
 288                 cr = makeCRField((int32_t)Ra_sd, simm, xer.so);
 289             }
 290         }});
 291     }
 292
 293     format IntImmCompLogicOp {
 294         10: cmpli({{
 295             if (length) {
 296                 cr = makeCRField(Ra, uimm, xer.so);
 297             } else {
 298                 cr = makeCRField((uint32_t)Ra, uimm, xer.so);
 299             }
 300         }});
 301      }
 302
 303     format IntImmLogicOp {
 304         24: ori({{ Ra = Rs | uimm; }});
 305         25: oris({{ Ra = Rs | (uimm << 16); }});
 306         26: xori({{ Ra = Rs ^ uimm; }});
 307         27: xoris({{ Ra = Rs ^ (uimm << 16); }});
 308         28: andi_({{ Ra = Rs & uimm; }},
 309                   true);
 310         29: andis_({{ Ra = Rs & (uimm << 16); }},
 311                    true);
 312     }
 313
 314     format IntRotateOp {
 315         21: rlwinm({{
 316             uint64_t res;
 317             res = rotate(Rs, shift);
 318             res = res & bitmask(maskBeg, maskEnd);
 319             Ra = res;
 320         }});
 321
 322         23: rlwnm({{
 323             uint64_t res;
 324             res = rotate(Rs, Rb);
 325             res = res & bitmask(maskBeg, maskEnd);
 326             Ra = res;
 327         }});
 328
 329         20: rlwimi({{
 330             uint64_t res, mask;
 331             mask = bitmask(maskBeg, maskEnd);
 332             res = rotate(Rs, shift);
 333             res = (res & mask) | (Ra & ~mask);
 334             Ra = res;
 335         }});
 336     }
 337
 338     // There are a large number of instructions that have the same primary
 339     // opcode (PO) of 31. In this case, the instructions are of different
 340     // forms. For every form, the XO fields may vary in position and width.
 341     // The X, XFL, XFX and XL form instructions use bits 21 - 30 and the
 342     // XO form instructions use bits 22 - 30 as extended opcode (XO). To
 343     // avoid conflicts, instructions of each form have to be defined under
 344     // separate decode blocks. However, only a single decode block can be
 345     // associated with a particular PO and it will recognize only one type
 346     // of XO field. A solution for associating decode blocks for the other
 347     // types of XO fields with the same PO is to have the other blocks as
 348     // nested default cases.
 349     31: decode X_XO {
 350
 351         // All loads with an index register. The non-update versions
 352         // all use the value 0 if Ra == R0, not the value contained in
 353         // R0. Others update Ra with the effective address. In all cases,
 354         // Ra and Rb are source registers, Rt is the destintation.
 355         format LoadIndexOp {
 356             87: lbzx({{ Rt = Mem_ub; }});
 357             52: lbarx({{ Rt = Mem_ub; Rsv = 1; RsvLen = 1; RsvAddr = EA; }});
 358             279: lhzx({{ Rt = Mem_uh; }});
 359             343: lhax({{ Rt = Mem_sh; }});
 360             116: lharx({{ Rt = Mem_uh; Rsv = 1; RsvLen = 2; RsvAddr = EA; }});
 361             790: lhbrx({{ Rt = swap_byte(Mem_uh); }});
 362             23: lwzx({{ Rt = Mem_uw; }});
 363             341: lwax({{ Rt = Mem_sw; }});
 364             20: lwarx({{ Rt = Mem_uw; Rsv = 1; RsvLen = 4; RsvAddr = EA; }});
 365             534: lwbrx({{ Rt = swap_byte(Mem_uw); }});
 366             21: ldx({{ Rt = Mem; }});
 367             84: ldarx({{ Rt = Mem_ud; Rsv = 1; RsvLen = 8; RsvAddr = EA; }});
 368             532: ldbrx({{ Rt = swap_byte(Mem); }});
 369             535: lfsx({{ Ft_sf = Mem_sf; }});
 370             599: lfdx({{ Ft = Mem_df; }});
 371             855: lfiwax({{ Ft_uw = Mem; }});
 372         }
 373
 374         format LoadIndexUpdateOp {
 375             119: lbzux({{ Rt = Mem_ub; }});
 376             311: lhzux({{ Rt = Mem_uh; }});
 377             375: lhaux({{ Rt = Mem_sh; }});
 378             55: lwzux({{ Rt = Mem_uw; }});
 379             373: lwaux({{ Rt = Mem_sw; }});
 380             53: ldux({{ Rt = Mem; }});
 381             567: lfsux({{ Ft_sf = Mem_sf; }});
 382             631: lfdux({{ Ft = Mem_df; }});
 383         }
 384
 385         format StoreIndexOp {
 386             215: stbx({{ Mem_ub = Rs_ub; }});
 387             694: stbcx({{
 388                 bool store_performed = false;
 389                 Mem_ub = Rs_ub;
 390                 if (Rsv) {
 391                     if (RsvLen == 1) {
 392                         if (RsvAddr == EA) {
 393                             store_performed = true;
 394                         }
 395                     }
 396                 }
 397                 Xer xer = XER;
 398                 Cr cr = CR;
 399                 cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
 400                 CR = cr;
 401                 Rsv = 0;
 402             }});
 403             407: sthx({{ Mem_uh = Rs_uh; }});
 404             726: sthcx({{
 405                 bool store_performed = false;
 406                 Mem_uh = Rs_uh;
 407                 if (Rsv) {
 408                     if (RsvLen == 2) {
 409                         if (RsvAddr == EA) {
 410                             store_performed = true;
 411                         }
 412                     }
 413                 }
 414                 Xer xer = XER;
 415                 Cr cr = CR;
 416                 cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
 417                 CR = cr;
 418                 Rsv = 0;
 419             }});
 420             918: sthbrx({{ Mem_uh = swap_byte(Rs_uh); }});
 421             151: stwx({{ Mem_uw = Rs_uw; }});
 422             150: stwcx({{
 423                 bool store_performed = false;
 424                 Mem_uw = Rs_uw;
 425                 if (Rsv) {
 426                     if (RsvLen == 4) {
 427                         if (RsvAddr == EA) {
 428                             store_performed = true;
 429                         }
 430                     }
 431                 }
 432                 Xer xer = XER;
 433                 Cr cr = CR;
 434                 cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
 435                 CR = cr;
 436                 Rsv = 0;
 437             }});
 438             662: stwbrx({{ Mem_uw = swap_byte(Rs_uw); }});
 439             149: stdx({{ Mem = Rs }});
 440             214: stdcx({{
 441                 bool store_performed = false;
 442                 Mem = Rs;
 443                 if (Rsv) {
 444                     if (RsvLen == 8) {
 445                         if (RsvAddr == EA) {
 446                             store_performed = true;
 447                         }
 448                     }
 449                 }
 450                 Xer xer = XER;
 451                 Cr cr = CR;
 452                 cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
 453                 CR = cr;
 454                 Rsv = 0;
 455             }});
 456             660: stdbrx({{ Mem = swap_byte(Rs); }});
 457         }
 458
 459         format StoreIndexUpdateOp {
 460             247: stbux({{ Mem_ub = Rs_ub; }});
 461             439: sthux({{ Mem_uh = Rs_uh; }});
 462             183: stwux({{ Mem_uw = Rs_uw; }});
 463             181: stdux({{ Mem = Rs; }});
 464         }
 465
 466         format IntArithOp {
 467             779: modsw({{
 468                 int64_t src1 = Ra_sw;
 469                 int64_t src2 = Rb_sw;
 470                 if ((src1 != INT32_MIN || src2 != -1) && src2 != 0) {
 471                     Rt = src1 % src2;
 472                 } else {
 473                     Rt = 0;
 474                 }
 475             }});
 476
 477             267: moduw({{
 478                 uint64_t src1 = Ra_uw;
 479                 uint64_t src2 = Rb_uw;
 480                 if (src2 != 0) {
 481                     Rt = src1 % src2;
 482                 } else {
 483                     Rt = 0;
 484                 }
 485             }});
 486
 487             777: modsd({{
 488                 int64_t src1 = Ra_sd;
 489                 int64_t src2 = Rb_sd;
 490                 if ((src1 != INT64_MIN || src2 != -1) && src2 != 0) {
 491                     Rt = src1 % src2;
 492                 } else {
 493                     Rt = 0;
 494                 }
 495             }});
 496
 497             265: modud({{
 498                 uint64_t src1 = Ra;
 499                 uint64_t src2 = Rb;
 500                 if (src2 != 0) {
 501                     Rt = src1 % src2;
 502                 } else {
 503                     Rt = 0;
 504                 }
 505             }});
 506         }
 507
 508         format IntCompOp {
 509             0: cmp({{
 510                 if (length) {
 511                     cr = makeCRField(Ra_sd, Rb_sd, xer.so);
 512                 } else {
 513                     cr = makeCRField((int32_t)Ra_sd, (int32_t)Rb_sd, xer.so);
 514                 }
 515             }});
 516
 517             32: cmpl({{
 518                 if (length) {
 519                     cr = makeCRField(Ra, Rb, xer.so);
 520                 } else {
 521                     cr = makeCRField((uint32_t)Ra, (uint32_t)Rb, xer.so);
 522                 }
 523             }});
 524
 525             192: cmprb({{
 526                 uint32_t src1 = Ra_ub;
 527                 uint32_t src2 = Rb_uw;
 528                 uint8_t src2lo = src2 & 0xff;
 529                 uint8_t src2hi = (src2 >>= 8) & 0xff;
 530                 uint32_t res = (src2lo <= src1) & (src1 <= src2hi);
 531                 if (length) {
 532                     src2lo = (src2 >>= 8) & 0xff;
 533                     src2hi = (src2 >>= 8) & 0xff;
 534                     res = ((src2lo <= src1) & (src1 <= src2hi)) | res;
 535                 }
 536                 cr = res << 2;
 537             }});
 538
 539             224: cmpeqb({{
 540                 const uint64_t m1 = 0x0101010101010101;
 541                 const uint64_t m2 = 0x8080808080808080;
 542                 uint64_t res = Rb ^ (Ra_ub * m1);
 543                 res = (res - m1) & ~res & m2;
 544                 cr = (res != 0) << 2;
 545             }});
 546         }
 547
 548         // Generic integer format instructions.
 549         format IntOp {
 550             339: decode SPR {
 551                 0x004: mftfhar({{ Rt = TFHAR; }});
 552                 0x008: mfvrsave({{ Rt = VRSAVE; }});
 553                 0x018: mfsier({{Rt = SIER;}});
 554                 0x019: mfbescrs({{Rt = BESCRS;}});
 555                 0x01C: mfppr({{ Rt = PPR; }});
 556                 0x020: mfxer({{ Rt = XER; }});
 557                 0x024: mftfiar({{ Rt = TFIAR; }});
 558                 0x039: mfbescrsu({{Rt = BESCRSU;}});
 559                 0x044: mftexasr({{ Rt = TEXASR; }});
 560                 0x05C: mfppr2({{ Rt =PPR32; }});
 561                 0x078: mfupmc1({{Rt = PMC1;}});
 562                 0x098: mfupmc2({{Rt = PMC2;}});
 563                 0x099: mfebbhr({{Rt = EBBHR;}});
 564                 0x0b8: mfupmc3({{Rt = PMC3;}});
 565                 0x0b9: mfebbrr({{Rt = EBBRR;}});
 566                 0x0d8: mfupmc4({{Rt = PMC4;}});
 567                 0x0d9: mfbescr({{Rt = BESCR;}});
 568                 0x0f8: mfupmc5({{Rt = PMC5;}});
 569                 0x100: mflr({{ Rt = LR; }});
 570                 0x104: mfctrl({{ Rt = CTRL; }});
 571                 0x118: mfupmc6r({{Rt = PMC6;}});
 572                 0x120: mfctr({{ Rt = CTR; }});
 573                 0x188: mftb({{ Rt = TB; }});
 574                 0x1A8: mftbu({{ Rt = TBU; }});
 575                 0x1b8: mfsdar({{Rt = SDAR;}});
 576                 0x1f9: mftar({{Rt = TAR;}});
 577                 0x204: mftidr({{ Rt = TIDR; }}, [ IsPrivileged ]);
 578                 0x205: mfdpdes({{ Rt = DPDES; }}, [ IsPrivileged ]);
 579                 0x208: mfsprg0({{Rt = SPRG0;}});
 580                 0x209: mfhsprg0({{Rt = HSPRG0;}});
 581                 0x20a: mfhmer({{Rt = HMER;}});
 582                 0x20E: mfptcr({{ Rt = PTCR; }});
 583                 0x219: mfasdr({{Rt = ASDR;}});
 584                 0x21a: mfic({{Rt = IC;}}, [ IsPrivileged ]);
 585                 0x21f: mfhir0({{Rt = HIR0;}});
 586                 0x220: mfdscr({{ Rt = DSCR; }});
 587                 0x228: mfsprg1({{Rt = SPRG1;}});
 588                 0x229: mfhsprg1({{Rt = HSPRG1;}});
 589                 0x22a: mfhmeer({{Rt = HMEER;}});
 590                 0x23a: mfvtb({{Rt = VTB;}}, [ IsPrivileged ]);
 591                 0x240: mfdsisr({{ Rt = DSISR; }});
 592                 0x248: mfsprg2({{Rt = SPRG2;}});
 593                 0x249: mfhdisr({{Rt = HDSISR;}});
 594                 0x24a: mfpcr({{Rt = PCR;}});
 595                 0x260: mfdar({{ Rt = DAR; }});
 596                 0x268: mfsprg3({{Rt = SPRG3;}});
 597                 0x269: mfhdar({{Rt = HDAR;}});
 598                 0x285: mfdawr0({{ Rt = DAWR0; }});
 599                 0x289: mfspurr({{Rt = SPURR;}}, [ IsPrivileged ]);
 600                 0x2a9: mfpurr({{Rt = PURR;}}, [ IsPrivileged ]);
 601                 0x2C0: mfdec({{ Rt = DEC; }});
 602                 0x2c9: mfhdec({{Rt = HDEC;}});
 603                 0x2fa: mfpsscr({{Rt = PSSCR;}});
 604                 0x324: mffscr({{Rt = FSCR;}});
 605                 0x329: mfhrmor({{Rt = HRMOR;}});
 606                 0x340: mfsrr0({{ Rt = SRR0; }});
 607                 0x345: mfrpr({{ Rt = RPR; }});
 608                 0x349: mfhssr0({{Rt = HSRR0;}});
 609                 0x360: mfsrr1({{ Rt = SRR1; }});
 610                 0x365: mfciabr({{ Rt = CIABR; }});
 611                 0x368: mfcir({{Rt = CIR;}}, [ IsPrivileged ]);
 612                 0x369: mfhssr1({{Rt = HSRR1;}});
 613                 0x380: mfcfar({{ Rt = CFAR; }});
 614                 0x3a0: mfamr({{ Rt = AMR; }}, [ IsPrivileged ]);
 615                 0x3a1: mfiamr({{Rt = IAMR;}});
 616                 0x3a4: mfuamor({{ Rt = UAMOR; }}, [ IsPrivileged ]);
 617                 0x3aa: mfamor({{Rt = AMOR;}});
 618                 0x3c5: mfhfscr({{Rt = HFSCR;}});
 619                 0x3c9: mflpcr({{Rt = LPCR;}});
 620                 0x3E8: mfpvr({{ Rt = PVR; }});
 621                 0x3e9: mflpidr({{Rt = LPIDR;}});
 622
 623             }
 624             467: decode SPR {
 625                 0x004: mttfhar({{TFHAR = Rs;}});
 626                 0x008: mtvrsave({{ VRSAVE = Rs; }});
 627                 0x019: mtbescrs({{BESCRS = Rs;}});
 628                 0x01C: mtppr({{ PPR = Rs; }});
 629                 0x020: mtxer({{ XER = Rs; }});
 630                 0x024: mttfiar({{TFIAR = Rs;}});
 631                 0x039: mtbescrsu({{BESCRSU = Rs;}});
 632                 0x044: mttexasr({{TEXASR = Rs;}});
 633                 0x05C: mtppr32({{ PPR32 = Rs; }});
 634                 0x078: mtupmc1({{PMC1 = Rs;}});
 635                 0x098: mtupmc2({{PMC2 = Rs;}});
 636                 0x099: mtebbhr({{EBBHR = Rs;}});
 637                 0x0b8: mtupmc3({{PMC3 = Rs;}});
 638                 0x0b9: mtebbrr({{EBBRR = Rs;}});
 639                 0x0d8: mtupmc4({{PMC4 = Rs;}});
 640                 0x0d9: mtbescr({{BESCR = Rs;}});
 641                 0x0f8: mtupmc5({{PMC5 = Rs;}});
 642                 0x100: mtlr({{ LR = Rs; }});
 643                 0x118: mtupmc6({{PMC6 = Rs;}});
 644                 0x120: mtctr({{ CTR = Rs; }});
 645                 0x1A8: mttbu({{ TBU = Rs; }});
 646                 0x1f9: mttar({{TAR = Rs;}});
 647                 0x201: mtpidr({{PIDR = Rs;}});
 648                 0x204: mttidr({{TIDR = Rs;}}, [ IsPrivileged ]);
 649                 0x205: mtdpdes({{DPDES = Rs;}});
 650                 0x208: mtsprg0({{SPRG0 = Rs;}});
 651                 0x209: mthsprg0({{HSPRG0 = Rs;}});
 652                 0x20a: mthmer({{HMER = Rs;}});
 653                 0x20E: mtptcr({{ PTCR = Rs; }});
 654                 0x219: mtasdr({{ASDR = Rs;}});
 655                 0x21a: mtic({{IC = Rs;}});
 656                 0x21f: mthir0({{HIR0 = Rs;}});
 657                 0x220: mtdscr({{ DSCR = Rs; }});
 658                 0x228: mtsprg1({{SPRG1 = Rs;}});
 659                 0x229: mthsprg1({{HSPRG1 = Rs;}});
 660                 0x22a: mthmeer({{HMEER = Rs;}});
 661                 0x238: mtmmcr2({{MMCR2 = Rs;}});
 662                 0x23a: mtvtb({{VTB = Rs;}});
 663                 0x240: mtdsisr({{ DSISR = Rs; }});
 664                 0x248: mtsprg2({{SPRG2 = Rs;}});
 665                 0x249: mthdisr({{HDSISR = Rs;}});
 666                 0x24a: mtpcr({{PCR = Rs;}});
 667                 0x258: mtmmcra({{MMCRA = Rs;}});
 668                 0x260: mtdar({{ DAR = Rs; }});
 669                 0x268: mtsprg3({{SPRG3 = Rs;}});
 670                 0x269: mthdar({{HDAR = Rs;}});
 671                 0x27a: mtmmcrc({{MMCRC = Rs;}});
 672                 0x285: mtdawr0({{DAWR0 = Rs;}});
 673                 0x289: mtspurr({{SPURR = Rs;}});
 674                 0x2a9: mtpurr({{PURR = Rs;}});
 675                 0x2C0: mtdec({{ DEC = Rs; }});
 676                 0x2c9: mthdec({{HDEC = Rs;}});
 677                 0x2fa: mtpsscr({{PSSCR = Rs;}});
 678                 0x304: mtctrl({{ CTRL = Rs; }});
 679                 0x324: mtfscr({{FSCR = Rs;}});
 680                 0x329: mthrmor({{HRMOR = Rs;}});
 681                 0x340: mtsrr0({{ SRR0 = Rs; }});
 682                 0x345: mtrpr({{RPR = Rs;}});
 683                 0x349: mthssr0({{HSRR0 = Rs;}});
 684                 0x360: mtsrr1({{ SRR1 = Rs; }});
 685                 0x365: mtciabr({{CIABR = Rs;}});
 686                 0x369: mthssr1({{HSRR1 = Rs;}});
 687                 0x378: mtmmcr0({{MMCR0 = Rs;}});
 688                 0x380: mtcfar({{ CFAR = Rs; }});
 689                 0x390: mttbl({{ TBL = Rs; }});
 690                 0x3a0: mtamr({{AMR = Rs;}}, [ IsPrivileged ]);
 691                 0x3a1: mtiamr({{IAMR = Rs;}});
 692                 0x3a4: mtuamor({{UAMOR = Rs;}}, [ IsPrivileged ]);
 693                 0x3aa: mtamor({{AMOR = Rs;}});
 694                 0x3c5: mthfscr({{HFSCR = Rs;}});
 695                 0x3c8: mttbu40({{TBU40 = Rs;}});
 696                 0x3c9: mtlpcr({{LPCR = Rs;}});
 697                 0x3d8: mtmmcr1({{MMCR1 = Rs;}});
 698                 0x3e9: mtlpidr({{LPIDR = Rs;}});
 699             }
 700
 701             83: mfmsr({{ Rt = MSR; }}, [ IsPrivileged ]);
 702
 703             178: mtmsrd({{
 704                 if (L == 0 ) {
 705                     uint64_t val = bits(Rs, 34, 32);
 706
 707                      if(bits(MSR, 34, 32) != 0x2 || val != 0x0) {
 708                       MSR =  insertBits(MSR, 34, 32, val);
 709                     }
 710
 711                     val = bits(Rs, 14);
 712
 713                     MSR = insertBits(MSR,  5,  bits(Rs, 5) | val);
 714                     MSR = insertBits(MSR,  4,  bits(Rs, 4) | val);
 715
 716                     MSR = insertBits(MSR, 63, 61, bits(Rs, 63, 61));
 717                     MSR = insertBits(MSR, 59, 35, bits(Rs, 59, 35));
 718                     MSR = insertBits(MSR, 31, 16, bits(Rs, 31, 16));
 719                     MSR = insertBits(MSR, 14, 13, bits(Rs, 14, 13));
 720                     MSR = insertBits(MSR, 11,  6, bits(Rs, 11,  6));
 721                     MSR = insertBits(MSR,  3,  1, bits(Rs,  3,  1));
 722                 } else {
 723                     MSR = insertBits(MSR, 15, bits(Rs, 15));
 724                     MSR = insertBits(MSR,  1, bits(Rs,  1));
 725                 }
 726             }}, [ IsPrivileged ]);
 727
 728             146: mtmsr({{
 729                  if( L ==0 ){
 730                      MSR = insertBits(MSR,15,bits(Rs,15)|bits(Rs,14));
 731                      MSR = insertBits(MSR,5,bits(Rs,5)|bits(Rs,14));
 732                      MSR = insertBits(MSR,4,bits(Rs,4)|bits(Rs,14));
 733                      MSR = insertBits(MSR,31,16,bits(Rs,31,16));
 734                      MSR = insertBits(MSR,14,13,bits(Rs,14,13));
 735                      MSR = insertBits(MSR,11,6,bits(Rs,11,6));
 736                      MSR = insertBits(MSR,3,1,bits(Rs,3,1));
 737                  }
 738                  else{
 739                      MSR = insertBits(MSR,15,bits(Rs,15));
 740                      MSR = insertBits(MSR,1,bits(Rs,1));
 741                  }
 742             }}, [ IsPrivileged ]);
 743         }
 744
 745         // Integer logic instructions use source registers Rs and Rb,
 746         // with destination register Ra.
 747         format IntLogicOp {
 748             28: and({{ Ra = Rs & Rb; }}, true);
 749             316: xor({{ Ra = Rs ^ Rb; }}, true);
 750             476: nand({{ Ra = ~(Rs & Rb); }}, true);
 751             444: or({{ Ra = Rs | Rb; }}, true);
 752             124: nor({{ Ra = ~(Rs | Rb); }}, true);
 753             60: andc({{ Ra = Rs & ~Rb; }}, true);
 754             284: eqv({{ Ra = ~(Rs ^ Rb); }}, true);
 755             412: orc({{ Ra = Rs | ~Rb; }}, true);
 756             954: extsb({{ Ra = Rs_sb; }}, true);
 757             922: extsh({{ Ra = Rs_sh; }}, true);
 758             986: extsw({{ Ra = Rs_sw; }}, true);
 759             26: cntlzw({{ Ra = findLeadingZeros(Rs_uw); }}, true);
 760             58: cntlzd({{ Ra = findLeadingZeros(Rs); }}, true);
 761             538: cnttzw({{ Ra = findTrailingZeros(Rs_uw); }}, true);
 762             570: cnttzd({{ Ra = findTrailingZeros(Rs); }}, true);
 763
 764             508: cmpb({{
 765                 uint64_t mask = 0xff;
 766                 uint64_t res = 0;
 767                 for (int i = 0; i < 8; ++i) {
 768                     if ((Rs & mask) == (Rb & mask)) {
 769                         res |= mask;
 770                     }
 771                     mask <<= 8;
 772                 }
 773                 Ra = res;
 774             }});
 775
 776             122: popcntb({{
 777                 const uint64_t m1 = 0x5555555555555555ULL;
 778                 const uint64_t m2 = 0x3333333333333333ULL;
 779                 const uint64_t m4 = 0x0f0f0f0f0f0f0f0fULL;
 780                 uint64_t res = Rs;
 781                 res = (res & m1) + ((res >> 1) & m1);
 782                 res = (res & m2) + ((res >> 2) & m2);
 783                 res = (res & m4) + ((res >> 4) & m4);
 784                 Ra = res;
 785             }});
 786
 787             378: popcntw({{
 788                 const uint64_t m1 = 0x5555555555555555ULL;
 789                 const uint64_t m2 = 0x3333333333333333ULL;
 790                 const uint64_t m4 = 0x0f0f0f0f0f0f0f0fULL;
 791                 const uint64_t m8 = 0x00ff00ff00ff00ffULL;
 792                 const uint64_t m16 = 0x0000ffff0000ffffULL;
 793                 uint64_t res = Rs;
 794                 res = (res & m1) + ((res >> 1) & m1);
 795                 res = (res & m2) + ((res >> 2) & m2);
 796                 res = (res & m4) + ((res >> 4) & m4);
 797                 res = (res & m8) + ((res >> 8) & m8);
 798                 res = (res & m16) + ((res >> 16) & m16);
 799                 Ra = res;
 800             }});
 801
 802             506: popcntd({{ Ra = popCount(Rs); }});
 803
 804             154: prtyw({{
 805                 uint64_t res = Rs;
 806                 res = res ^ (res >> 16);
 807                 res = res ^ (res >> 8);
 808                 res = res & 0x100000001;
 809                 Ra = res;
 810             }});
 811
 812             186: prtyd({{
 813                 uint64_t res = Rs;
 814                 res = res ^ (res >> 32);
 815                 res = res ^ (res >> 16);
 816                 res = res ^ (res >> 8);
 817                 res = res & 0x1;
 818                 Ra = res;
 819             }});
 820
 821             252: bpermd({{
 822                 uint64_t res = 0;
 823                 for (int i = 0; i < 8; ++i) {
 824                     int index = (Rs >> (i * 8)) & 0xff;
 825                     if (index < 64) {
 826                         if (Rb & (1ULL << (63 - index))) {
 827                             res |= 1 << i;
 828                         }
 829                     }
 830                 }
 831                 Ra = res;
 832             }});
 833         }
 834
 835         // Integer instructions with a shift value.
 836         format IntShiftOp {
 837             24: slw({{
 838                 int32_t shift = Rb_sw;
 839                 uint32_t res = Rs_uw & ~((shift << 26) >> 31);
 840                 if (shift != 0) {
 841                     shift = shift & 0x1f;
 842                     res = res << shift;
 843                 }
 844                 Ra = res;
 845             }});
 846
 847             536: srw({{
 848                 int32_t shift = Rb_sw;
 849                 uint32_t res = Rs_uw & ~((shift << 26) >> 31);
 850                 if (shift != 0) {
 851                     shift = shift & 0x1f;
 852                     res = res >> shift;
 853                 }
 854                 Ra = res;
 855             }});
 856
 857             792: sraw({{
 858                 int32_t src = Rs_sw;
 859                 uint32_t shift = Rb_uw;
 860                 int64_t res;
 861                 if ((shift & 0x20) != 0) {
 862                     res = src >> 31;
 863                     if (res != 0) {
 864                         setCA = true;
 865                     }
 866                 } else {
 867                     if (shift != 0) {
 868                         shift = shift & 0x1f;
 869                         res = src >> shift;
 870                         if (src < 0 && (src & mask(shift)) != 0) {
 871                             setCA = true;
 872                         }
 873                     } else {
 874                         res = src;
 875                     }
 876                 }
 877                 Ra = res;
 878             }},
 879             true);
 880
 881             824: srawi({{
 882                 int32_t src = Rs_sw;
 883                 int64_t res;
 884                 if (shift != 0) {
 885                     res = src >> shift;
 886                     if (src < 0 && (src & mask(shift)) != 0) {
 887                         setCA = true;
 888                     }
 889                 } else {
 890                     res = src;
 891                 }
 892                 Ra = res;
 893             }},
 894             true);
 895         }
 896
 897         format IntConcatShiftOp {
 898             27: sld({{
 899                 int64_t shift = Rb_sd;
 900                 uint64_t res = Rs & ~((shift << 57) >> 63);
 901                 if (shift != 0) {
 902                     shift = shift & 0x3f;
 903                     res = res << shift;
 904                 }
 905                 Ra = res;
 906             }});
 907
 908             539: srd({{
 909                 int64_t shift = Rb_sd;
 910                 uint64_t res = Rs & ~((shift << 57) >> 63);
 911                 if (shift != 0) {
 912                     shift = shift & 0x3f;
 913                     res = res >> shift;
 914                 }
 915                 Ra = res;
 916             }});
 917
 918             794: srad({{
 919                 int64_t src = Rs_sd;
 920                 uint64_t shift = Rb;
 921                 int64_t res;
 922                 if ((shift & 0x40) != 0) {
 923                     res = src >> 63;
 924                     if (res != 0) {
 925                         setCA = true;
 926                     }
 927                 } else {
 928                     if (shift != 0) {
 929                         shift = shift & 0x3f;
 930                         res = src >> shift;
 931                         if (src < 0 && (src & mask(shift)) != 0) {
 932                             setCA = true;
 933                         }
 934                     } else {
 935                         res = src;
 936                     }
 937                 }
 938                 Ra = res;
 939             }},
 940             true);
 941         }
 942
 943         format StoreIndexOp {
 944             663: stfsx({{ Mem_sf = Fs_sf; }});
 945             727: stfdx({{ Mem_df = Fs; }});
 946             983: stfiwx({{ Mem = Fs_uw; }});
 947         }
 948
 949         format StoreIndexUpdateOp {
 950             695: stfsux({{ Mem_sf = Fs_sf; }});
 951             759: stfdux({{ Mem_df = Fs; }});
 952         }
 953
 954         // These instructions all provide data cache hints
 955         format MiscOp {
 956             278: dcbt({{ }});
 957             246: dcbtst({{ }});
 958             598: sync({{ }}, [ IsMemBarrier ]);
 959             854: eieio({{ }}, [ IsMemBarrier ]);
 960             54:  dcbst({{ }});
 961             982: icbi({{ }});
 962             306: tlbie({{ }});
 963             274: tlbiel({{ }}, [ IsPrivileged ]);
 964             566: tlbsync({{ }});
 965             498: slbia({{ }}, [ IsPrivileged ]);
 966         }
 967
 968         // These instructions are of XO form with bit 21 as the OE bit.
 969         default: decode XO_XO {
 970
 971             // These instructions can all be reduced to the form
 972             // Rt = src1 + src2 [+ CA], therefore we just give src1 and src2
 973             // (and, if necessary, CA) definitions and let the python script
 974             // deal with setting things up correctly. We also give flags to
 975             // say which control registers to set.
 976             format IntSumOp {
 977                 266: add({{ Ra }}, {{ Rb }});
 978                 40: subf({{ ~Ra }}, {{ Rb }}, {{ 1 }});
 979                 10: addc({{ Ra }}, {{ Rb }},
 980                          computeCA = true);
 981                 8: subfc({{ ~Ra }}, {{ Rb }}, {{ 1 }},
 982                          true);
 983                 104: neg({{ ~Ra }}, {{ 1 }});
 984                 138: adde({{ Ra }}, {{ Rb }}, {{ xer.ca }},
 985                           true);
 986                 234: addme({{ Ra }}, {{ -1ULL }}, {{ xer.ca }},
 987                            true);
 988                 136: subfe({{ ~Ra }}, {{ Rb }}, {{ xer.ca }},
 989                            true);
 990                 232: subfme({{ ~Ra }}, {{ -1ULL }}, {{ xer.ca }},
 991                             true);
 992                 202: addze({{ Ra }}, {{ xer.ca }},
 993                            computeCA = true);
 994                 200: subfze({{ ~Ra }}, {{ xer.ca }},
 995                             computeCA = true);
 996             }
 997
 998             // Arithmetic instructions all use source registers Ra and Rb,
 999             // with destination register Rt.
1000             format IntArithCheckRcOp {
1001                 75: mulhw({{
1002                     uint64_t res = (int64_t)Ra_sw * Rb_sw;
1003                     res = res >> 32;
1004                     Rt = res;
1005                 }});
1006
1007                 11: mulhwu({{
1008                     uint64_t res = (uint64_t)Ra_uw * Rb_uw;
1009                     res = res >> 32;
1010                     Rt = res;
1011                 }});
1012
1013                 235: mullw({{
1014                     int64_t res = (int64_t)Ra_sw * Rb_sw;
1015                     if (res != (int32_t)res) {
1016                         setOV = true;
1017                     }
1018                     Rt = res;
1019                 }},
1020                 true);
1021
1022                 73: mulhd({{
1023                     int64_t res;
1024                     std::tie(std::ignore, res) = multiply(Ra_sd, Rb_sd);
1025                     Rt = res;
1026                 }});
1027
1028                 9: mulhdu({{
1029                     uint64_t res;
1030                     std::tie(std::ignore, res) = multiply(Ra, Rb);
1031                     Rt = res;
1032                 }});
1033
1034                 233: mulld({{
1035                     int64_t src1 = Ra_sd;
1036                     int64_t src2 = Rb_sd;
1037                     uint64_t res = src1 * src2;
1038                     std::tie(res, std::ignore) = multiply(src1, src2);
1039                     if (src1 != 0 && (int64_t)res / src1 != src2) {
1040                         setOV = true;
1041                     }
1042                     Rt = res;
1043                 }},
1044                 true);
1045
1046                 491: divw({{
1047                     int32_t src1 = Ra_sw;
1048                     int32_t src2 = Rb_sw;
1049                     if ((src1 != INT32_MIN || src2 != -1) && src2 != 0) {
1050                         Rt = (uint32_t)(src1 / src2);
1051                     } else {
1052                         Rt = 0;
1053                         setOV = true;
1054                     }
1055                 }},
1056                 true);
1057
1058                 459: divwu({{
1059                     uint32_t src1 = Ra_uw;
1060                     uint32_t src2 = Rb_uw;
1061                     if (src2 != 0) {
1062                         Rt = src1 / src2;
1063                     } else {
1064                         Rt = 0;
1065                         setOV = true;
1066                     }
1067                 }},
1068                 true);
1069
1070                 427: divwe({{
1071                     int32_t src1 = Ra_sw;
1072                     int32_t src2 = Rb_sw;
1073                     int64_t res;
1074                     if ((src1 != INT32_MIN || src2 != -1) && src2 != 0) {
1075                         res = ((int64_t)src1 << 32) / src2;
1076                         if (res == (int32_t)res) {
1077                             Rt = (uint32_t)res;
1078                         } else {
1079                             Rt = 0;
1080                             setOV = true;
1081                         }
1082                     } else {
1083                         Rt = 0;
1084                         setOV = true;
1085                     }
1086                 }},
1087                 true);
1088
1089                 395: divweu({{
1090                     uint32_t src1 = Ra_ud;
1091                     uint32_t src2 = Rb_ud;
1092                     uint64_t res;
1093                     if (src2 != 0) {
1094                         res = ((uint64_t)src1 << 32) / src2;
1095                         if (res <= UINT32_MAX) {
1096                             Rt = (uint32_t)res;
1097                         } else {
1098                             Rt = 0;
1099                             setOV = true;
1100                         }
1101                     } else {
1102                         Rt = 0;
1103                         setOV = true;
1104                     }
1105                 }},
1106                 true);
1107
1108                 489: divd({{
1109                     int64_t src1 = Ra_sd;
1110                     int64_t src2 = Rb_sd;
1111                     if ((src1 != INT64_MIN || src2 != -1) && src2 != 0) {
1112                         Rt = src1 / src2;
1113                     } else {
1114                         Rt = 0;
1115                         setOV = true;
1116                     }
1117                 }},
1118                 true);
1119
1120                 457: divdu({{
1121                     uint64_t src1 = Ra;
1122                     uint64_t src2 = Rb;
1123                     if (src2 != 0) {
1124                         Rt = src1 / src2;
1125                     } else {
1126                         Rt = 0;
1127                         setOV = true;
1128                     }
1129                 }},
1130                 true);
1131
1132                 425: divde({{
1133                     int64_t src1 = Ra_sd;
1134                     int64_t src2 = Rb_sd;
1135                     int64_t res;
1136                     std::tie(setOV, res, std::ignore) = divide(0, src1, src2);
1137                     if (!setOV) {
1138                         Rt = res;
1139                     } else {
1140                         Rt = 0;
1141                     }
1142                 }},
1143                 true);
1144
1145                 393: divdeu({{
1146                     uint64_t src1 = Ra;
1147                     uint64_t src2 = Rb;
1148                     uint64_t res;
1149                     std::tie(setOV, res, std::ignore) = divide(0, src1, src2);
1150                     if (!setOV) {
1151                         Rt = res;
1152                     } else {
1153                         Rt = 0;
1154                     }
1155                 }},
1156                 true);
1157             }
1158
1159             // These instructions are of XS form and use bits 21 - 29 as XO.
1160             default: decode XS_XO {
1161                 format IntConcatShiftOp {
1162                     413: sradi({{
1163                         int64_t src = Rs_sd;
1164                         if (shift != 0) {
1165                             Ra = src >> shift;
1166                             if (src < 0 && (src & mask(shift))) {
1167                                 setCA = true;
1168                             }
1169                         } else {
1170                             Ra = src;
1171                         }
1172                     }},
1173                     true);
1174
1175                     445: extswsli({{
1176                         int64_t src = Rs_sw;
1177                         if (shift != 0) {
1178                             Ra = src << shift;
1179                         } else {
1180                             Ra = src;
1181                         }
1182                     }});
1183                 }
1184
1185                 default: decode XFX_XO {
1186                     format IntOp {
1187                         144: mtcrf({{
1188                             uint32_t mask = 0;
1189                             for (int i = 0; i < 8; ++i) {
1190                                 if (((FXM >> i) & 0x1) == 0x1) {
1191                                     mask |= 0xf << (4 * i);
1192                                 }
1193                             }
1194                             CR = (Rs & mask) | (CR & ~mask);
1195                         }});
1196
1197                         19: mfcr({{ Rt = CR; }});
1198                     }
1199                 }
1200             }
1201         }
1202     }
1203
1204     // These instructions are of MD form and use bits 27 - 29 as XO.
1205     30: decode MD_XO {
1206         format IntConcatRotateOp {
1207             0: rldicl({{
1208                 uint64_t res;
1209                 if (shift != 0) {
1210                     res = rotate(Rs, shift);
1211                 } else {
1212                     res = Rs;
1213                 }
1214                 res = res & bitmask(maskBeg, 63);
1215                 Ra = res;
1216             }});
1217
1218             1: rldicr({{
1219                 uint64_t res;
1220                 if (shift != 0) {
1221                     res = rotate(Rs, shift);
1222                 } else {
1223                     res = Rs;
1224                 }
1225                 res = res & bitmask(0, maskEnd);
1226                 Ra = res;
1227             }});
1228
1229             2: rldic({{
1230                 uint64_t res;
1231                 if (shift != 0) {
1232                     res = rotate(Rs, shift);
1233                 } else {
1234                     res = Rs;
1235                 }
1236                 res = res & bitmask(maskBeg, ~shift);
1237                 Ra = res;
1238             }});
1239
1240             3: rldimi({{
1241                 uint64_t res, mask;
1242                 mask = bitmask(maskBeg, ~shift);
1243                 if (shift != 0) {
1244                     res = rotate(Rs, shift);
1245                 } else {
1246                     res = Rs;
1247                 }
1248                 res = res & mask;
1249                 res = res | (Ra & ~mask);
1250                 Ra = res;
1251             }});
1252
1253             // These instructions are of MDS form and use bits 27 - 30 as XO.
1254             default: decode MDS_XO {
1255                 8: rldcl({{
1256                     uint64_t res;
1257                     uint32_t shift = Rb & 0x3f;
1258                     if (shift != 0) {
1259                         res = rotate(Rs, shift);
1260                     } else {
1261                         res = Rs;
1262                     }
1263                     res = res & bitmask(maskBeg, 63);
1264                     Ra = res;
1265                 }});
1266
1267                 9: rldcr({{
1268                     uint64_t res;
1269                     uint32_t shift = Rb & 0x3f;
1270                     if (shift != 0) {
1271                         res = rotate(Rs, shift);
1272                     } else {
1273                         res = Rs;
1274                     }
1275                     res = res & bitmask(0, maskEnd);
1276                     Ra = res;
1277                 }});
1278             }
1279         }
1280     }
1281
1282     format LoadDispOp {
1283         48: lfs({{ Ft_sf = Mem_sf; }});
1284         50: lfd({{ Ft = Mem_df; }});
1285     }
1286
1287     format LoadDispUpdateOp {
1288         49: lfsu({{ Ft_sf = Mem_sf; }});
1289         51: lfdu({{ Ft = Mem_df; }});
1290     }
1291
1292     format StoreDispOp {
1293         52: stfs({{ Mem_sf = Fs_sf; }});
1294         54: stfd({{ Mem_df = Fs; }});
1295     }
1296
1297     format StoreDispUpdateOp {
1298         53: stfsu({{ Mem_sf = Fs_sf; }});
1299         55: stfdu({{ Mem_df = Fs; }});
1300     }
1301
1302     format FloatArithOp {
1303         59: decode A_XO {
1304             21: fadds({{ Ft = Fa + Fb; }});
1305             20: fsubs({{ Ft = Fa - Fb; }});
1306             25: fmuls({{ Ft = Fa * Fc; }});
1307             18: fdivs({{ Ft = Fa / Fb; }});
1308             29: fmadds({{ Ft = (Fa * Fc) + Fb; }});
1309             28: fmsubs({{ Ft = (Fa * Fc) - Fb; }});
1310             31: fnmadds({{ Ft = -((Fa * Fc) + Fb); }});
1311             30: fnmsubs({{ Ft = -((Fa * Fc) - Fb); }});
1312         }
1313     }
1314
1315     63: decode A_XO {
1316         format FloatArithOp {
1317             21: fadd({{ Ft = Fa + Fb; }});
1318             20: fsub({{ Ft = Fa - Fb; }});
1319             25: fmul({{ Ft = Fa * Fc; }});
1320             18: fdiv({{ Ft = Fa / Fb; }});
1321             29: fmadd({{ Ft = (Fa * Fc) + Fb; }});
1322             28: fmsub({{ Ft = (Fa * Fc) - Fb; }});
1323             31: fnmadd({{ Ft = -((Fa * Fc) + Fb); }});
1324             30: fnmsub({{ Ft = -((Fa * Fc) - Fb); }});
1325         }
1326
1327         default: decode X_XO {
1328             format FloatRCCheckOp {
1329                 72: fmr({{ Ft = Fb; }});
1330                 264: fabs({{
1331                     Ft_ud = Fb_ud;
1332                     Ft_ud = insertBits(Ft_ud, 63, 0); }});
1333                 136: fnabs({{
1334                     Ft_ud = Fb_ud;
1335                     Ft_ud = insertBits(Ft_ud, 63, 1); }});
1336                 40: fneg({{ Ft = -Fb; }});
1337                 8: fcpsgn({{
1338                     Ft_ud = Fb_ud;
1339                     Ft_ud = insertBits(Ft_ud, 63, Fa_ud<63:63>);
1340                 }});
1341             }
1342
1343             format FloatConvertOp {
1344                 12: frsp({{ Ft_sf = Fb; }});
1345                 15: fctiwz({{ Ft_sw = (int32_t)trunc(Fb); }});
1346             }
1347
1348             format FloatOp {
1349               0: fcmpu({{
1350                   uint32_t c = makeCRField(Fa, Fb);
1351                   Fpscr fpscr = FPSCR;
1352                   fpscr.fprf.fpcc = c;
1353                   FPSCR = fpscr;
1354                   CR = insertCRField(CR, BF, c);
1355               }});
1356             }
1357
1358             format FloatRCCheckOp {
1359                 583: mffs({{ Ft_ud = FPSCR; }});
1360                 134: mtfsfi({{
1361                     FPSCR = insertCRField(FPSCR, BF + (8 * (1 - W_FIELD)),
1362                                           U_FIELD);
1363                 }});
1364                 70: mtfsb0({{ FPSCR = insertBits(FPSCR, 31 - BT, 0); }});
1365                 38: mtfsb1({{ FPSCR = insertBits(FPSCR, 31 - BT, 1); }});
1366
1367                 default: decode XFL_XO {
1368                     711: mtfsf({{
1369                         if (L_FIELD == 1) { FPSCR = Fb_ud; }
1370                         else {
1371                             for (int i = 0; i < 8; ++i) {
1372                                 if (bits(FLM, i) == 1) {
1373                                     int k = 4 * (i + (8 * (1 - W_FIELD)));
1374                                     FPSCR = insertBits(FPSCR, k + 3, k,
1375                                                        bits(Fb_ud, k + 3, k));
1376                                 }
1377                             }
1378                         }
1379                     }});
1380                 }
1381             }
1382         }
1383     }
1384 }