3 // Copyright (c) 2009 The University of Edinburgh
4 // All rights reserved.
6 // Redistribution and use in source and binary forms, with or without
7 // modification, are permitted provided that the following conditions are
8 // met: redistributions of source code must retain the above copyright
9 // notice, this list of conditions and the following disclaimer;
10 // redistributions in binary form must reproduce the above copyright
11 // notice, this list of conditions and the following disclaimer in the
12 // documentation and/or other materials provided with the distribution;
13 // neither the name of the copyright holders nor the names of its
14 // contributors may be used to endorse or promote products derived from
15 // this software without specific prior written permission.
17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 // Authors: Timothy M. Jones
31 ////////////////////////////////////////////////////////////////////
33 // The actual Power ISA decoder
34 // ------------------------------
36 // I've used the Power ISA Book I v2.06 for instruction formats,
37 // opcode numbers, register names, etc.
39 decode OPCODE default Unknown::unknown() {
44 uint32_t cr = makeCRField(Ra, (uint32_t)uimm, xer.so);
45 CR = insertCRField(CR, BF, cr);
49 uint32_t cr = makeCRField(Ra_sw, (int32_t)imm, xer.so);
50 CR = insertCRField(CR, BF, cr);
54 // Some instructions use bits 21 - 30, others 22 - 30. We have to use
55 // the larger size to account for all opcodes. For those that use the
56 // smaller value, the OE bit is bit 21. Therefore, we have two versions
57 // of each instruction: 1 with OE set, the other without. For an
58 // example see 'add' and 'addo'.
61 // These instructions can all be reduced to the form
62 // Rt = src1 + src2 [+ CA], therefore we just give src1 and src2
63 // (and, if necessary, CA) definitions and let the python script
64 // deal with setting things up correctly. We also give flags to
65 // say which control registers to set.
67 266: add({{ Ra }}, {{ Rb }});
68 40: subf({{ ~Ra }}, {{ Rb }}, {{ 1 }});
69 10: addc({{ Ra }}, {{ Rb }},
71 8: subfc({{ ~Ra }}, {{ Rb }}, {{ 1 }},
73 104: neg({{ ~Ra }}, {{ 1 }});
74 138: adde({{ Ra }}, {{ Rb }}, {{ xer.ca }},
76 234: addme({{ Ra }}, {{ (uint32_t)-1 }}, {{ xer.ca }},
78 136: subfe({{ ~Ra }}, {{ Rb }}, {{ xer.ca }},
80 232: subfme({{ ~Ra }}, {{ (uint32_t)-1 }}, {{ xer.ca }},
82 202: addze({{ Ra }}, {{ xer.ca }},
84 200: subfze({{ ~Ra }}, {{ xer.ca }},
88 // Arithmetic instructions all use source registers Ra and Rb,
89 // with destination register Rt.
91 75: mulhw({{ int64_t prod = Ra_sd * Rb_sd; Rt = prod >> 32; }});
92 11: mulhwu({{ uint64_t prod = Ra_ud * Rb_ud; Rt = prod >> 32; }});
93 235: mullw({{ int64_t prod = Ra_sd * Rb_sd; Rt = prod; }});
97 int64_t prod = src1 * src2;
103 int32_t src1 = Ra_sw;
104 int32_t src2 = Rb_sw;
105 if ((src1 != 0x80000000 || src2 != 0xffffffff)
114 int32_t src1 = Ra_sw;
115 int32_t src2 = Rb_sw;
116 if ((src1 != 0x80000000 || src2 != 0xffffffff)
127 uint32_t src1 = Ra_sw;
128 uint32_t src2 = Rb_sw;
137 uint32_t src1 = Ra_sw;
138 uint32_t src2 = Rb_sw;
149 // Integer logic instructions use source registers Rs and Rb,
150 // with destination register Ra.
152 28: and({{ Ra = Rs & Rb; }});
153 316: xor({{ Ra = Rs ^ Rb; }});
154 476: nand({{ Ra = ~(Rs & Rb); }});
155 444: or({{ Ra = Rs | Rb; }});
156 124: nor({{ Ra = ~(Rs | Rb); }});
157 60: andc({{ Ra = Rs & ~Rb; }});
158 954: extsb({{ Ra = sext<8>(Rs); }});
159 284: eqv({{ Ra = ~(Rs ^ Rb); }});
160 412: orc({{ Ra = Rs | ~Rb; }});
161 922: extsh({{ Ra = sext<16>(Rs); }});
162 26: cntlzw({{ Ra = Rs == 0 ? 32 : 31 - findMsbSet(Rs); }});
165 for (int n = 0; n < 32; n += 8) {
166 if(bits(Rs, n+7, n) == bits(Rb, n+7, n)) {
167 val = insertBits(val, n+7, n, 0xff);
177 Ra = Rs << (Rb & 0x1f);
185 Ra = Rs >> (Rb & 0x1f);
190 bool shiftSetCA = false;
195 } else if (Rb & 0x20) {
198 if (s & 0x7fffffff) {
208 Ra = s >> (Rb & 0x1f);
209 if (s < 0 && (s << (32 - (Rb & 0x1f))) != 0) {
225 // Integer logic instructions with a shift value.
228 bool shiftSetCA = false;
235 if (s < 0 && (s << (32 - sh)) != 0) {
251 // Generic integer format instructions.
255 uint32_t cr = makeCRField(Ra_sw, Rb_sw, xer.so);
256 CR = insertCRField(CR, BF, cr);
260 uint32_t cr = makeCRField(Ra, Rb, xer.so);
261 CR = insertCRField(CR, BF, cr);
265 for (int i = 0; i < 8; ++i) {
266 if (((FXM >> i) & 0x1) == 0x1) {
267 mask |= 0xf << (4 * i);
270 CR = (Rs & mask) | (CR & ~mask);
272 19: mfcr({{ Rt = CR; }});
274 0x20: mfxer({{ Rt = XER; }});
275 0x100: mflr({{ Rt = LR; }});
276 0x120: mfctr({{ Rt = CTR; }});
279 0x20: mtxer({{ XER = Rs; }});
280 0x100: mtlr({{ LR = Rs; }});
281 0x120: mtctr({{ CTR = Rs; }});
285 // All loads with an index register. The non-update versions
286 // all use the value 0 if Ra == R0, not the value contained in
287 // R0. Others update Ra with the effective address. In all cases,
288 // Ra and Rb are source registers, Rt is the destintation.
290 87: lbzx({{ Rt = Mem_ub; }});
291 279: lhzx({{ Rt = Mem_uh; }});
292 343: lhax({{ Rt = Mem_sh; }});
293 23: lwzx({{ Rt = Mem; }});
294 341: lwax({{ Rt = Mem_sw; }});
295 20: lwarx({{ Rt = Mem_sw; Rsv = 1; RsvLen = 4; RsvAddr = EA; }});
296 535: lfsx({{ Ft_sf = Mem_sf; }});
297 599: lfdx({{ Ft = Mem_df; }});
298 855: lfiwax({{ Ft_uw = Mem; }});
301 format LoadIndexUpdateOp {
302 119: lbzux({{ Rt = Mem_ub; }});
303 311: lhzux({{ Rt = Mem_uh; }});
304 375: lhaux({{ Rt = Mem_sh; }});
305 55: lwzux({{ Rt = Mem; }});
306 373: lwaux({{ Rt = Mem_sw; }});
307 567: lfsux({{ Ft_sf = Mem_sf; }});
308 631: lfdux({{ Ft = Mem_df; }});
311 format StoreIndexOp {
312 215: stbx({{ Mem_ub = Rs_ub; }});
313 407: sthx({{ Mem_uh = Rs_uh; }});
314 151: stwx({{ Mem = Rs; }});
316 bool store_performed = false;
321 store_performed = true;
327 cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
331 663: stfsx({{ Mem_sf = Fs_sf; }});
332 727: stfdx({{ Mem_df = Fs; }});
333 983: stfiwx({{ Mem = Fs_uw; }});
336 format StoreIndexUpdateOp {
337 247: stbux({{ Mem_ub = Rs_ub; }});
338 439: sthux({{ Mem_uh = Rs_uh; }});
339 183: stwux({{ Mem = Rs; }});
340 695: stfsux({{ Mem_sf = Fs_sf; }});
341 759: stfdux({{ Mem_df = Fs; }});
344 // These instructions all provide data cache hints
348 598: sync({{ }}, [ IsMemBarrier ]);
349 854: eieio({{ }}, [ IsMemBarrier ]);
353 format IntImmArithCheckRaOp {
354 14: addi({{ Rt = Ra + imm; }},
356 15: addis({{ Rt = Ra + (imm << 16); }},
357 {{ Rt = imm << 16; }});
360 format IntImmArithOp {
361 12: addic({{ uint32_t src = Ra; Rt = src + imm; }},
363 13: addic_({{ uint32_t src = Ra; Rt = src + imm; }},
364 [computeCA, computeCR0]);
365 8: subfic({{ int32_t src = ~Ra; Rt = src + imm + 1; }},
369 int64_t prod = src * imm;
374 format IntImmLogicOp {
375 24: ori({{ Ra = Rs | uimm; }});
376 25: oris({{ Ra = Rs | (uimm << 16); }});
377 26: xori({{ Ra = Rs ^ uimm; }});
378 27: xoris({{ Ra = Rs ^ (uimm << 16); }});
379 28: andi_({{ Ra = Rs & uimm; }},
381 29: andis_({{ Ra = Rs & (uimm << 16); }},
387 // Conditionally branch relative to PC based on CR and CTR.
388 format BranchPCRelCondCtr {
389 0: bc({{ NIA = (uint32_t)(CIA + disp); }});
392 // Conditionally branch to fixed address based on CR and CTR.
393 format BranchNonPCRelCondCtr {
394 1: bca({{ NIA = targetAddr; }});
400 // Unconditionally branch relative to PC.
402 0: b({{ NIA = (uint32_t)(CIA + disp); }});
405 // Unconditionally branch to fixed address.
406 format BranchNonPCRel {
407 1: ba({{ NIA = targetAddr; }});
413 // Conditionally branch to address in LR based on CR and CTR.
414 format BranchLrCondCtr {
415 16: bclr({{ NIA = LR & 0xfffffffc; }});
418 // Conditionally branch to address in CTR based on CR.
419 format BranchCtrCond {
420 528: bcctr({{ NIA = CTR & 0xfffffffc; }});
423 // Condition register manipulation instructions.
426 uint32_t crBa = bits(CR, 31 - ba);
427 uint32_t crBb = bits(CR, 31 - bb);
428 CR = insertBits(CR, 31 - bt, crBa & crBb);
431 uint32_t crBa = bits(CR, 31 - ba);
432 uint32_t crBb = bits(CR, 31 - bb);
433 CR = insertBits(CR, 31 - bt, crBa | crBb);
436 uint32_t crBa = bits(CR, 31 - ba);
437 uint32_t crBb = bits(CR, 31 - bb);
438 CR = insertBits(CR, 31 - bt, !(crBa & crBb));
441 uint32_t crBa = bits(CR, 31 - ba);
442 uint32_t crBb = bits(CR, 31 - bb);
443 CR = insertBits(CR, 31 - bt, crBa ^ crBb);
446 uint32_t crBa = bits(CR, 31 - ba);
447 uint32_t crBb = bits(CR, 31 - bb);
448 CR = insertBits(CR, 31 - bt, !(crBa | crBb));
451 uint32_t crBa = bits(CR, 31 - ba);
452 uint32_t crBb = bits(CR, 31 - bb);
453 CR = insertBits(CR, 31 - bt, crBa == crBb);
456 uint32_t crBa = bits(CR, 31 - ba);
457 uint32_t crBb = bits(CR, 31 - bb);
458 CR = insertBits(CR, 31 - bt, crBa & !crBb);
461 uint32_t crBa = bits(CR, 31 - ba);
462 uint32_t crBb = bits(CR, 31 - bb);
463 CR = insertBits(CR, 31 - bt, crBa | !crBb);
468 uint32_t crBfa = bits(CR, 31 - bfa*4, 28 - bfa*4);
469 CR = insertBits(CR, 31 - bf*4, 28 - bf*4, crBfa);
473 150: isync({{ }}, [ IsSerializeAfter ]);
478 21: rlwinm({{ Ra = rotateValue(Rs, sh) & fullMask; }});
479 23: rlwnm({{ Ra = rotateValue(Rs, Rb) & fullMask; }});
480 20: rlwimi({{ Ra = (rotateValue(Rs, sh) & fullMask) | (Ra & ~fullMask); }});
484 34: lbz({{ Rt = Mem_ub; }});
485 40: lhz({{ Rt = Mem_uh; }});
486 42: lha({{ Rt = Mem_sh; }});
487 32: lwz({{ Rt = Mem; }});
488 58: lwa({{ Rt = Mem_sw; }},
489 {{ EA = Ra + (disp & 0xfffffffc); }},
490 {{ EA = disp & 0xfffffffc; }});
491 48: lfs({{ Ft_sf = Mem_sf; }});
492 50: lfd({{ Ft = Mem_df; }});
495 format LoadDispUpdateOp {
496 35: lbzu({{ Rt = Mem_ub; }});
497 41: lhzu({{ Rt = Mem_uh; }});
498 43: lhau({{ Rt = Mem_sh; }});
499 33: lwzu({{ Rt = Mem; }});
500 49: lfsu({{ Ft_sf = Mem_sf; }});
501 51: lfdu({{ Ft = Mem_df; }});
505 38: stb({{ Mem_ub = Rs_ub; }});
506 44: sth({{ Mem_uh = Rs_uh; }});
507 36: stw({{ Mem = Rs; }});
508 52: stfs({{ Mem_sf = Fs_sf; }});
509 54: stfd({{ Mem_df = Fs; }});
512 format StoreDispUpdateOp {
513 39: stbu({{ Mem_ub = Rs_ub; }});
514 45: sthu({{ Mem_uh = Rs_uh; }});
515 37: stwu({{ Mem = Rs; }});
516 53: stfsu({{ Mem_sf = Fs_sf; }});
517 55: stfdu({{ Mem_df = Fs; }});
520 17: IntOp::sc({{ xc->syscall(R0, &fault); }},
521 [ IsSyscall, IsNonSpeculative, IsSerializeAfter ]);
523 format FloatArithOp {
525 21: fadds({{ Ft = Fa + Fb; }});
526 20: fsubs({{ Ft = Fa - Fb; }});
527 25: fmuls({{ Ft = Fa * Fc; }});
528 18: fdivs({{ Ft = Fa / Fb; }});
529 29: fmadds({{ Ft = (Fa * Fc) + Fb; }});
530 28: fmsubs({{ Ft = (Fa * Fc) - Fb; }});
531 31: fnmadds({{ Ft = -((Fa * Fc) + Fb); }});
532 30: fnmsubs({{ Ft = -((Fa * Fc) - Fb); }});
537 format FloatArithOp {
538 21: fadd({{ Ft = Fa + Fb; }});
539 20: fsub({{ Ft = Fa - Fb; }});
540 25: fmul({{ Ft = Fa * Fc; }});
541 18: fdiv({{ Ft = Fa / Fb; }});
542 29: fmadd({{ Ft = (Fa * Fc) + Fb; }});
543 28: fmsub({{ Ft = (Fa * Fc) - Fb; }});
544 31: fnmadd({{ Ft = -((Fa * Fc) + Fb); }});
545 30: fnmsub({{ Ft = -((Fa * Fc) - Fb); }});
548 default: decode XO_XO {
549 format FloatConvertOp {
550 12: frsp({{ Ft_sf = Fb; }});
551 15: fctiwz({{ Ft_sw = (int32_t)trunc(Fb); }});
556 uint32_t c = makeCRField(Fa, Fb);
560 CR = insertCRField(CR, BF, c);
564 format FloatRCCheckOp {
565 72: fmr({{ Ft = Fb; }});
568 Ft_ud = insertBits(Ft_ud, 63, 0); }});
571 Ft_ud = insertBits(Ft_ud, 63, 1); }});
572 40: fneg({{ Ft = -Fb; }});
575 Ft_ud = insertBits(Ft_ud, 63, Fa_ud<63:63>);
577 583: mffs({{ Ft_ud = FPSCR; }});
579 FPSCR = insertCRField(FPSCR, BF + (8 * (1 - W_FIELD)),
583 if (L_FIELD == 1) { FPSCR = Fb_ud; }
585 for (int i = 0; i < 8; ++i) {
586 if (bits(FLM, i) == 1) {
587 int k = 4 * (i + (8 * (1 - W_FIELD)));
588 FPSCR = insertBits(FPSCR, k + 3, k,
589 bits(Fb_ud, k + 3, k));
594 70: mtfsb0({{ FPSCR = insertBits(FPSCR, 31 - BT, 0); }});
595 38: mtfsb1({{ FPSCR = insertBits(FPSCR, 31 - BT, 1); }});