src/arch/power/isa/formats/util.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2003-2005 The Regents of The University of Michigan
   4 // Copyright (c) 2009 The University of Edinburgh
   5 // All rights reserved.
   6 //
   7 // Redistribution and use in source and binary forms, with or without
   8 // modification, are permitted provided that the following conditions are
   9 // met: redistributions of source code must retain the above copyright
  10 // notice, this list of conditions and the following disclaimer;
  11 // redistributions in binary form must reproduce the above copyright
  12 // notice, this list of conditions and the following disclaimer in the
  13 // documentation and/or other materials provided with the distribution;
  14 // neither the name of the copyright holders nor the names of its
  15 // contributors may be used to endorse or promote products derived from
  16 // this software without specific prior written permission.
  17 //
  18 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  21 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  24 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  25 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  26 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  28 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29
  30 // Some instructions ignore the contents of Ra if Ra == 0,
  31 // so check for this.
  32 def template CheckRaDecode {{
  33  {
  34      if (RA == 0) {
  35          return new %(class_name)sRaZero(machInst);
  36      } else {
  37          return new %(class_name)s(machInst);
  38      }
  39  }
  40 }};
  41
  42
  43 // Some instructions have extra behaviour if Rc is set.
  44 def template CheckRcDecode {{
  45  {
  46      if (RC31 == 0) {
  47          return new %(class_name)s(machInst);
  48      } else {
  49          return new %(class_name)sRcSet(machInst);
  50      }
  51  }
  52 }};
  53
  54
  55 // Some instructions have extra behaviour if Rc and OE are set.
  56 def template CheckRcOeDecode {{
  57  {
  58      if (RC31 == 0) {
  59          if (OE == 0) {
  60              return new %(class_name)s(machInst);
  61          } else {
  62              return new %(class_name)sOeSet(machInst);
  63          }
  64      } else {
  65          if (OE == 0) {
  66              return new %(class_name)sRcSet(machInst);
  67          } else {
  68              return new %(class_name)sRcSetOeSet(machInst);
  69          }
  70      }
  71  }
  72 }};
  73
  74 // Branch instructions always have two versions, one which sets the link
  75 // register (LR).
  76 def template CheckLkDecode {{
  77  {
  78      if (LK == 0) {
  79          return new %(class_name)s(machInst);
  80      } else {
  81          return new %(class_name)sUpdateLr(machInst);
  82      }
  83  }
  84 }};
  85
  86
  87 let {{
  88
  89 def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
  90                   base_class = 'MemOp',
  91                   decode_template = BasicDecode, exec_template_base = ''):
  92     # Make sure flags are in lists (convert to lists if not).
  93     mem_flags = makeList(mem_flags)
  94     inst_flags = makeList(inst_flags)
  95
  96     # Generate InstObjParams for the memory access.
  97     iop = InstObjParams(name, Name, base_class,
  98                         {'ea_code': ea_code,
  99                          'memacc_code': memacc_code},
 100                         inst_flags)
 101
 102     if mem_flags:
 103         s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
 104         iop.constructor += s
 105
 106     fullExecTemplate = eval(exec_template_base + 'Execute')
 107     initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
 108     completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
 109
 110     # (header_output, decoder_output, decode_block, exec_output)
 111     return (LoadStoreDeclare.subst(iop),
 112             LoadStoreConstructor.subst(iop),
 113             decode_template.subst(iop),
 114             fullExecTemplate.subst(iop)
 115             + initiateAccTemplate.subst(iop)
 116             + completeAccTemplate.subst(iop))
 117
 118
 119 # The generic ALU instruction generator. Integer and fp formats calls this
 120 # to generate the different output sections.
 121 def GenAluOp(name, Name, base_class, code, inst_flags, decode_template,
 122              constructor_template):
 123     iop = InstObjParams(name, Name, base_class,
 124                         {"code": code},
 125                         inst_flags)
 126     header_output = BasicDeclare.subst(iop)
 127     exec_output = BasicExecute.subst(iop)
 128
 129     # We use constructors dependent on the Rc and OE bits being set
 130     decoder_output = constructor_template.subst(iop)
 131
 132     # The decode block defines which version to use
 133     decode_block = decode_template.subst(iop)
 134     return (header_output, decoder_output, decode_block, exec_output)
 135
 136 }};
 137
 138
 139 output header {{
 140     std::string
 141     inst2string(MachInst machInst);
 142 }};
 143
 144 output decoder {{
 145
 146     std::string
 147     inst2string(MachInst machInst)
 148     {
 149         std::string str = "";
 150         uint32_t mask = 0x80000000;
 151
 152         for(int i=0; i < 32; i++) {
 153             if ((machInst & mask) == 0) {
 154                 str += "0";
 155             } else {
 156                 str += "1";
 157             }
 158
 159             mask = mask >> 1;
 160         }
 161
 162         return str;
 163     }
 164
 165 }};
 166
 167