arch: Templatize the BasicDecodeCache.
[gem5.git] / src / arch / power / isa.hh
1 /*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * Copyright (c) 2009 The University of Edinburgh
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30 #ifndef __ARCH_POWER_ISA_HH__
31 #define __ARCH_POWER_ISA_HH__
32
33 #include "arch/generic/isa.hh"
34 #include "arch/power/registers.hh"
35 #include "arch/power/types.hh"
36 #include "base/logging.hh"
37 #include "cpu/reg_class.hh"
38 #include "sim/sim_object.hh"
39
40 struct PowerISAParams;
41 class ThreadContext;
42 class Checkpoint;
43 class EventManager;
44
45 namespace PowerISA
46 {
47
48 class ISA : public BaseISA
49 {
50 protected:
51 RegVal dummy;
52 RegVal miscRegs[NumMiscRegs];
53
54 public:
55 typedef PowerISAParams Params;
56
57 void clear() {}
58
59 public:
60 RegVal
61 readMiscRegNoEffect(int misc_reg) const
62 {
63 fatal("Power does not currently have any misc regs defined\n");
64 return dummy;
65 }
66
67 RegVal
68 readMiscReg(int misc_reg)
69 {
70 fatal("Power does not currently have any misc regs defined\n");
71 return dummy;
72 }
73
74 void
75 setMiscRegNoEffect(int misc_reg, RegVal val)
76 {
77 fatal("Power does not currently have any misc regs defined\n");
78 }
79
80 void
81 setMiscReg(int misc_reg, RegVal val)
82 {
83 fatal("Power does not currently have any misc regs defined\n");
84 }
85
86 RegId flattenRegId(const RegId& regId) const { return regId; }
87
88 int
89 flattenIntIndex(int reg) const
90 {
91 return reg;
92 }
93
94 int
95 flattenFloatIndex(int reg) const
96 {
97 return reg;
98 }
99
100 int
101 flattenVecIndex(int reg) const
102 {
103 return reg;
104 }
105
106 int
107 flattenVecElemIndex(int reg) const
108 {
109 return reg;
110 }
111
112 int
113 flattenVecPredIndex(int reg) const
114 {
115 return reg;
116 }
117
118 // dummy
119 int
120 flattenCCIndex(int reg) const
121 {
122 return reg;
123 }
124
125 int
126 flattenMiscIndex(int reg) const
127 {
128 return reg;
129 }
130
131 const Params &params() const;
132
133 ISA(const Params &p);
134 };
135
136 } // namespace PowerISA
137
138 #endif // __ARCH_POWER_ISA_HH__